DAQ/PXI-201x/200x 4-CH, Simultaneous, High Performance Multi-Function Data Acquisition Card User’s Manual Manual Rev. 2.00 Revision Date: April 20, 2006 Part No: 50-11020-1030 Advance Technologies; Automate the World.
Copyright 2006 ADLINK TECHNOLOGY INC. All Rights Reserved. The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer. In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.
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Table of Contents 1 Introduction ........................................................................ 1 1.1 1.2 1.3 1.4 Features............................................................................... 2 Applications ......................................................................... 3 Specifications....................................................................... 4 Software Support ............................................................... 13 Programming Library ................
4.5 4.6 Trigger Sources ................................................................. 57 Software-Trigger ........................................................... 57 External Analog Trigger ................................................ 57 User-controllable Timing Signals ....................................... 61 DAQ timing signals ....................................................... 63 Auxiliary Function Inputs (AFI) ...................................... 64 System Synchronization Interface .
List of Tables Table Table Table Table Table Table Table Table 1-1: 1-2: 1-3: 3-1: 3-2: 3-3: 3-4: 4-1: Table 4-2: Table 4-3: Table 4-4: Table 4-5: Table 4-6: Table 4-7: Table 4-8: Table 4-9: Table 4-10: List of Tables -3dB small signal bandwidth ..................................... 5 System Noise ........................................................... 5 CMRR: (DC to 60Hz) ................................................ 7 68-pin VHDCI-type pin assignment ........................
List of Figures Figure 2-1: Figure 2-2: Figure 3-1: Figure 3-2: Figure 3-3: Figure 4-1: Figure 4-2: Figure 4-3: Figure 4-4: PCB Layout of the DAQ-20XX................................. 17 PCB Layout of the PXI-20XX................................... 17 Single-Ended connections ....................................... 25 Ground-referenced source and differential input ..... 25 Floating source and differential input....................... 26 Synchronous Digital Inputs Block Diagram..............
Figure 4-21: Stop mode II ............................................................ Figure 4-22: Stop mode III ........................................................... Figure 4-23: Mode 1 Operation.................................................... Figure 4-24: Mode 2 Operation.................................................... Figure 4-25: Mode 3 Operation.................................................... Figure 4-26: Mode 4 Operation....................................................
1 Introduction The DAQ/PXI-20XX is an advanced data acquisition card based on the 32-bit PCI architecture. High performance designs and the state-of-the-art technology make this card ideal for data logging and signal analysis ap-plications in medical, process control, etc.
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X -3dB small signal bandwidth: (Typical, 25°C) Device Input Range Bandwidth (-3dB) Input Range Bandwidth (-3dB) 2010 2005 2006 2016 ±10V 1170 kHz 0~10V 1090 kHz ±5V 1050 kHz 0~5V 1020 kHz ±2.5V 800 kHz 0~2.5V 790 kHz ±1.25V 530 kHz 0~1.25V 530 kHz ±10V 1160 kHz 0~10V 1210 kHz ±5V 1050 kHz 0~5V 1050 kHz ±2.5V 780 kHz 0~2.5V 770 kHz ±1.25V 520 kHz 0~1.25V 530 kHz ±10V 630 kHz 0~10V 640 kHz ±5V 620 kHz 0~5V 620 kHz ±2.5V 540 kHz 0~2.5V 540 kHz ±1.
Device Input Range System noise Input Range System noise 2006 2016 ±10V 1.0 LSBrms 0~10V 1.5 LSBrms ±5V 1.0 LSBrms 0~5V 1.6 LSBrms ±2.5V 1.1 LSBrms 0~2.5V 1.7 LSBrms ±1.25V 1.1 LSBrms 0~1.25V 1.8 LSBrms ±10V 1.6 LSBrms 0~10V 2.9 LSBrms ±5V 1.8 LSBrms 0~5V 3.2 LSBrms ±2.5V 1.8 LSBrms 0~2.5V 3.2 LSBrms ±1.25V 1.9 LSBrms 0~1.25V 3.
X CMRR: (DC to 60Hz, Typical) Device Input Range CMRR Input Range CMRR 2010 2005 2006 2016 ±10V 90 dB 0~10V 89 dB ±5V 92 dB 0~5V 92 dB ±2.5V 95 dB 0~2.5V 94 dB ±1.25V 97 dB 0~1.25V 97 dB ±10V 86 dB 0~10V 85 dB ±5V 88 dB 0~5V 88 dB ±2.5V 91 dB 0~2.5V 90 dB ±1.25V 93 dB 0~1.25V 93 dB ±10V 87 dB 0~10V 86 dB ±5V 89 dB 0~5V 88 dB ±2.5V 91 dB 0~2.5V 91 dB ±1.25V 93 dB 0~1.25V 93 dB ±10V 85dB 0~10V 86dB ±5V 88dB 0~5V 88dB ±2.5V 91dB 0~2.5V 92dB ±1.
8 Z Before calibration: ±0.6% of output max Z After calibration: ±0.1% of output max for DAQ/PXI2010, ±0.
Analog Output (AO) X Number of channels: 2 channel voltage output X DA converter: LTC7545 or equivalent X Max update rate: 1MS/s X Resolution: 12 bits X FIFO buffer size: Z X Data transfers: Z X 1k samples per channel when both channels are enabled for timed DA output, and 2k samples when only one channel is used for timed DA output Programmed I/O, and bus-mastering DMA with scatter/ gather Output range: Z Bipolar: ±10V or ±AOEXTREF Z Unipolar: 0~10V or 0~AOEXTREF X Settling time: 3µS to
Z Before calibration: ±0.8% of output max Z After calibration: ±0.02% of output max X General Purpose Digital I/O (G.P. DIO, 82C55A) X Number of channels: 24 programmable Input/Output X Compatibility: TTL/CMOS X Input voltage: X Z Logic Low: VIL=0.8V max; IIL=0.2mA max. Z High: VIH=2.0V max; IIH=0.02mA max Output voltage: Z Low: VOL=0.5V max; IOL=8mA max. Z High: VOH=2.
Analog Trigger (A.Trig) X Source: Z All analog input channels; external analog trigger (EXTATRIG) X Level: ±Full-scale, internal; ±10V external X Resolution: 8 bits X Slope: Positive or negative (software selectable) X Hysteresis: Programmable X Bandwidth: 400khz External Analog Trigger Input (EXTATRIG) X Input Impedance: Z 40kΩ for DAQ/PXI-2010 Z 2kΩ for DAQ/PXI-2005/2006/2016 X Coupling: DC X Protection: Continuous ±35V maximum Digital Trigger (D.
Physical X X Dimensions: Z 175mm by 107mm for DAQ-20XX Z Standard CompactPCI form factor for PXI-20XX I/O connector: 68-pin female VHDCI type (e.g. AMP787254-1) Power Requirement (typical) X +5VDC: 1.82 A for DAQ/PXI-2010 Z 2.04 A for DAQ/PXI-2005 Z 1.82 A for DAQ/PXI-2006 Z 2.
1.4 Software Support ADLINK provides versatile software drivers and packages for users’ dif-ferent approach to building up a system. ADLINK not only provides pro-gramming libraries such as DLL for most Windows based systems, but also provide drivers for other software packages such as LabVIEW®. All software options are included in the ADLINK CD. Non-free software drivers are protected with licensing codes.
license. For detailed information about DAQ-LVIEW PnP, please refer to the user’s guide in the CD. (\\Manual\Software Package\DAQ-LVIEW PnP) D2K-OCX: ActiveX Controls We suggest customers who are familiar with ActiveX controls and VB/VC++ programming use D2K-OCX ActiveX control component libraries for developing applications. D2K-OCX is designed for Windows 98/NT/2000/XP. For more detailed information about D2K-OCX, please refer to the user's guide in the CD.
2 Installation This chapter describes how to install the DAQ/PXI-20XX. The contents of the package and unpacking information that you should be aware of are outlined first. The DAQ/PXI-20XX performs an automatic configuration of the IRQ, and port address. Users can use software utility, PCI_SCAN to read the system configuration. 2.
Again, inspect the module for damages. Press down on all the socketed IC's to make sure that they are properly seated. Do this only with the module place on a firm flat surface. You are now ready to install your DAQ/PXI-20XX. Note: 16 DO NOT APPLY POWER TO THE CARD IF IT HAS BEEN DAMAGED.
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2.4 PCI Configuration 1. Plug and Play: As a plug and play component, the card requests an interrupt number via its PCI controller. The system BIOS responds with an interrupt assignment based on the card information and on known system parameters. These system parameters are determined by the installed drivers and the hardware load seen by the system. 2. Configuration: The board configuration is done on a board-by-board basis for all PCI boards on your system.
3 Signal Connections This chapter describes the connectors of the DAQ/PXI-20XX, and the signal connection between the DAQ/PXI-20XX and external devices. 3.1 Connectors Pin Assignment The DAQ/PXI-20XX is equipped with one 68-pin VHDCI-type connector (AMP-787254-1). It is used for digital input/output, analog input / output, and timer/counter signals, etc. One 20-pin ribbon male connector is used for SSI (System Synchronous Interface) in DAQ-20XX.
PB7 22 56 PB6 PB5 23 57 PB4 PB3 24 58 PB2 PB1 25 59 PB0 PC7 26 60 PC6 PC5 27 61 PC4 DGND 28 62 DGND PC3 29 63 PC2 PC1 30 64 PC0 PA7 31 65 PA6 PA5 32 66 PA4 PA3 33 67 PA2 PA1 34 68 PA0 Table 3-1: 68-pin VHDCI-type pin assignment * SDI for DAQ/PXI-2010 only; NC for DAQ/PXI-2005/2006/2016 Legend: Pin # Signal Name Reference Direction Description 1~4 CH<0..3>+ CH0<0..3>- Input Differential positive input for AI channel <0..
Pin # Signal Name Reference Direction Description 17,51 GPTC<0,1>_GATE DGND Input Gate of GPTC<0,1> 18,52 GPTC<0,1>_OUT DGND Input Output of GPTC<0,1> 19,53 GPTC<0,1>_UPDOWN DGND Input Up/Down of GPTC<0,1> 20 EXTTIMEBASE DGND Input External TIMEBASE 21,28,49,50,54,62 DGND -------- -------- Digital ground 22,56,23,57,24,58,25,59 PB<7,0> DGND PIO* Programmable DIO pins of 8255 Port B 26,60,27,61,29,63,30,64 PC<7,0> DGND PIO* Programmable DIO pins of 8255 Port C 31,65,32,
Pin # Signal Name 21 Reference Direction AFI1 DGND Input Description Auxiliary Function Input 1 (DAWR, DA_START) Table 3-2: 68-pin VHDCI-type Connector Legend *PIO means programmable I/O SSI_TIMEBASE 1 2 DGND SSI_ADCONV 3 4 DGND SSI_DAWR 5 6 DGND SSI_SCAN_START 7 8 DGND RESERVED 9 10 DGND SSI_AD_TRIG 11 12 DGND SSI_DA_TRIG 13 14 DGND RESERVED 15 16 DGND RESERVED 17 18 DGND RESERVED 19 20 DGND Table 3-3: SSI connector (JP3) pin assignment for DAQ-20XX Legend: SSI timing s
SSI timing signal Functionality SSI_DAWR SSI master: send the DAWR out. SSI slave: accept the SSI_DAWR to replace the internal DAWR signal. SSI_DA_TRIG SSI master: send the DA_TRIG out. SSI slave: accept the SSI_DA_TRIG as the digital trigger signal.
3.2 Analog Input Signal Connection The DAQ/PXI-20XX provides 4 differential analog input channels. The analog signal can be converted to digital values by the A/D converter. To avoid ground loops and get more accurate measurements from the A/D conversion, it is quite important to understand the signal source type and how to connect the analog input signals. Types of signal sources Ground-Referenced Signal Sources A ground-referenced signal means it is connected in some way to the building system.
Figure 3-1: Single-Ended connections In single-ended configurations, more electrostatic and magnetic noise couples into the single connections than in differential configurations. Therefore, the single-ended connection is not recommended unless minimal wire connections are necessary. Differential Measurements Differential Sources Connection for Grounded-Reference Signal The differential analog input provides two inputs that respond to the signal voltage difference between them.
Differential Connection for Floating Signal Sources Figure 3-3 shows how to connect a floating signal source to DAQ/PXI-20XX in differential input mode. For floating signal sources, you need to add a resistor at each channel to provide a bias return path. The resistor value should be about 100 times the equivalent source impedance.
4 Operation Theory The operation theory of the functions on the DAQ/PXI-20XX is described in this chapter. The functions include the A/D conversion, D/A conversion, Digital I/O and General Purpose Counter/ Timer. The operation theory can help you understand how to configure and program the DAQ/PXI-20XX. The whole DAQ/PXI-2000 series cards, including DAQ/PXI-20XX, DAQ/PXI-22XX and DAQ/PXI-25XX, are designed based on the same logic-timing template of DAQ/PXI-22XX.
DAQ/PXI-2010 AI Data Format Synchronous Digital Inputs (for DAQ/PXI-2010 only) When each A/D conversion is completed, the 14-bits converted digital data accompanied with 2 bits of SDI<1..0>_X per channel from J5 will be latched into the 16-bit register and data FIFO, as shown in Figure 8 and Figure 9. Therefore, users can simultaneously sample one analog signal with four digital signals. The data format of every acquired 16-bit data is as follows: D13, D12, D11 ....... D1, D0, b1, b0 Where D13, D12, D11 ...
due to the variation of the conver-sion time of the A/D converters. Table 4-1 and 4-2 illustrate the ideal transfer characteristics of various input ranges of DAQ\PXI-20XX. The converted digital codes for DAQ\PXI-2010 are 14-bit and 2’s complement, and here we present the codes as hexa-decimal numbers. Note that the last 2 bits of the transferred data, which are the synchronous digital input (SDI), should be ignored when retrieving the analog data.
DAQ/PXI-2005/2006/2016 AI Data Format The data format of the acquired 16-bit A/D data is Binary coding. Table 7 and 8 illustrate the valid input ranges and the ideal transfer characteristics. The converted digital codes for DAQ/PXI-2005/ 2006/2016 are 16-bit and direct binary, and here we present the codes as hexadecimal numbers. Description Full-scale Range Least significant bit FSR-1LSB Bipolar Analog Input Range Digital code ±10V ±5V ±2.5V ±1.25V 305.2uV 152.6uV 76.3uV 38.15uV 9.999695V 4.
This method is very suitable for applications that needs to process A/D data in real time. Under this mode, the timing of the A/D conversion is fully controlled under software. However, it is difficult to control the A/D con-version rate. Specifying Channel, Gain, and Polarity In both the Software Polling and programmable scan acquisition mode, the channel, gain, and polarity for each channel can be specified and selected.
pling A/D card, so the “scan interval” equals to the “sampling interval”. Example: (Post-trigger acquisition) Set SI_counter = 160 PSC_counter = 30 TIMEBASE = Internal clock source Then Scan Interval = 160/40M s = 4 us Total acquisition time = 30 X 4 us = 120 us TIMEBASE clock source In scan acquisition mode, all the A/D conversions start on the output of counters, which use TIMEBASE as the clock source.
There are 4 trigger modes to start the scan acquisition, please refer to section 4.1for more details. The data transfer mode is discussed below. Note: 1. The maximum A/D sampling rate is 2MHz for DAQ/PXI2010, 500kHz for DAQ/PXI-2005, 250kHz for DAQ/PXI2006 and 800kHz for DAQ/PXI-2016. Therefore, the minimum setting of SI_counter is 20 for DAQ/PXI-2010, 80 for DAQ/PXI-2005, 160 for DAQ/PXI-2006 and 50 for DAQ/PXI-2016 while using the internal TIMEBASE. 2. The SI_counter is a 24-bit counter.
post scan count is 0 because there is no sampling after the trigger event in pre-trigger acquisition. The total stored amount of data = Number of enabled channels * M_counter.
This situation can be avoided by setting M_enable. If M_enable is set to 1, the trigger signal will be ignored until the first M scans of data are converted, and it assures the user M scans of data under pre-trigger mode, as illustrated in Figure 4-7. However, if M_enable is set to 0, the trigger signal will be accepted any time, as illustrated in Figure 13.
Note: The PSC_counter is set to 0 in pre-trigger acquisition mode. Middle-Trigger Acquisition Use middle-trigger acquisition in applications where you want to collect data before and after a trigger event. The number of scans (M) stored before the trigger is specified in M_counter, while the number of scans (N) after the trigger is specified in PSC_counter.
If the trigger event occurs when a scan is in progress, the stored N scans of data would include this scan, as illustrated in Figure 4-9. Figure 4-9: Middle trigger (trigger occurs when a scan is in progress) Note:M_counter defined in Middle-Trigger is different from that of Pre-Trigger. In Middle-trigger, M_Counter ends counting before the trigger event while in Pre-Trigger, M_Counter ends counting right at or before trigger event. Please refer to Figure 4-6 and Figure 4-9.
Figure 4-10: Post trigger Delay Trigger Acquisition Use delay trigger acquisition in applications where you want to delay the data collection after the occurrence of a specified trigger event. The delay time is controlled by the value, which is pre-loaded in the Delay_counter (16bit). The counter counts down on the rising edge of the Delay_counter clock source after the trigger condition is met.
data. The total acquired data length = number of enable-channel * PSC_counter. Figure 4-11: Delay trigger Note: When the Delay_counter clock source is set to TIMEBASE, the maximum delay time = 216/40M s = 1.638ms, and when the source is set to A/D sampling clock, the maximum delay time can be as higher as (216 * SI_counter / 40M ).
Figure 4-12: Post trigger with re-trigger Bus-mastering DMA Data Transfer PCI bus-mastering DMA is necessary for high speed DAQ in order to utilize the maximum PCI bandwidth. The bus-mastering controller, which is built in the PLX IOP-480 PCI controller, controls the PCI bus when it becomes the master of the bus. Bus mastering reduces the size of the on-board memory and reduces the CPU loading because data is directly transferred to the computer’s memory without host CPU intervention.
please refer to http://www.plxtech.com for more in-formation on PCI controllers. By using a high-level programming library for high speed DMA data ac-quisition, users simply need to assign the sampling period and the number of conversion into their specified counters. After the AD trigger condition is matched, the data will be transferred to the system memory by the bus-mastering DMA.
Figure 4-13: Scatter/gather DMA for data transfer In non-chaining mode, the maximum DMA data transfer size is 2M double words (8M bytes). However, by using chaining mode, scatter/gather, there is no limitation on DMA data transfer size. Users can also link the de-scriptor nodes circularly to achieve a multibuffered mode DMA. 4.2 D/A Conversion There are 2 channels of 12-bit D/A output available in the DAQ/ PXI-20XX.
put by feeding a sinusoidal signal into the reference input. The range of the external reference should be within ±10V. Table 4-5 and 4-6 illustrates the relationship between digital code and output voltages.
bipolar, and ref-erence source: internal 10V or external AOEXTREF. Then update the digital values into D/A data registers through a software output command. Timed Waveform Generation This mode can provide your applications with a precise D/A output with a fixed update rate. It can be used to generate an infinite or finite waveform. You can accurately program the update period of the D/A converters. The D/A output timing is provided through a combination of counters in the FPGA on board.
Figure 21 shows a typical D/A timing diagram. D/A updates its output on each rising edge of DAWR. The meaning of the counters above is dis-cussed more in the following sections. Figure 4-14: Typical D/A timing of waveform generation (Assuming the data in the data buffer are 2V, 4V, -4V, 0V) Note: The maximum D/A update rate is 1MHz. Therefore, the minimum setting of the UI_counter is 40 while using an internal TIMEBASE(40MHz).
Figure 4-15: Post trigger waveform generation (Assuming the data in the data buffer are 2V, 4V, 6V, 3V, 0V, -4V, -2V, 4V) Delay-Trigger Generation Use delay trigger when you want to delay the waveform generation after a trigger event. In Figure 4-16, DA_DLY1_counter determines the delay time from the trigger signal to the start of the waveform generation. DLY1_counter counts down on the rising edge of its clock source after the trigger condition is met.
Figure 4-16: Delay trigger waveform generation (Assuming the data in the data buffer are 2V, 4V, 6V, 3V, 0V, -4V, -2V, 4V) Post-Trigger or Delay-Trigger with Re-trigger Use post-trigger or delay-trigger with re-trigger function when you want to generate waveform after more than one trigger events. The re-trigger function can be enabled or disabled by software setting. In Figure 4-17, each trigger signal will initiate a waveform generation.
Iterative Waveform Generation Set IC_Counter in order to generate iterative waveforms from the data of a single waveform. The counter stores the iteration number, and the itera-tions can be finite (Figure 4-12) or infinite (Figure 4-13). A data FIFO on board is used to buffer the digital data for DA output.
Figure 4-19: Infinite iterative waveform generation with Post-trigger and DLY2_Counter = 0 (Assuming the data in the data buffer are 2V, 4V, 2V, 0V) Note: 1. When running infinite iterative waveform generation, setting IC_Counter is ineffective to the waveform generation. It only makes a difference when setting stop mode III, please refer to section 4.2.2.3. 2. How to set finite and infinite iterative waveform generation is not in-cluded in this manual.
for timed waveform gen-eration, which means when it is to stop the waveform generation. You can apply these 3 modes to stop waveform generation no matter infinite or finite waveform generation mode is selected. Figure 4-20 illustrates an example for stop mode I, in this mode the waveform stops immediately when software command is asserted. In stop mode II, after a software stop command is given, the waveform generation won’t stop until a complete single waveform is finished.
Figure 4-21: Stop mode II Figure 4-22: Stop mode III 4.3 Digital I/O The DAQ/PXI-20XX contains 24-lines of general-purpose digital I/ O (GPIO), which is provided through a 82C55A chip. The 24-line GPIO are separated into three ports: Port A, Port B and Port C. High nibble (bit[7…4]), and low nibble (bit[3…0]) of each port can be indi-vidually programmed to be either inputs or outputs. Upon system startup or reset, all the GPIO pins are reset to high impedance inputs.
input and is stored with the 14-bit AD data. Please refer to section 4.1 for the more details. 4.4 General Purpose Timer/Counter Operation Two independent 16-bit up/down timer/counter are designed within FPGA for various applications.
GPTC_GATE, and GPTC_OUT are assumed to be active high or rising-edge triggered in the figures. General Purpose Timer/Counter modes Eight programmable timer/counter modes are provided. All modes start operating following a software-start signal that is set by the software. The GPTC software reset initializes the status of the counter and re-loads the initial value to the counter. The operation remains halted until the soft-ware-start is re-executed.
4-24 il-lustrates the operation where initial count = 0, count-up mode. Figure 4-24: Mode 2 Operation Mode 3: Single Pulse-width Measurement In this mode the counter counts the pulse-width of the signal on GPTC_GATE in terms of GPTC_CLK. Initial count can be loaded from software. After the software-start, the counter counts the number of active edges on GPTC_CLK when GPTC_GATE is in its active state.
GPTC_GATE is used to enable/disable counting. When GPTC_GATE is inactive, the counter halts the current count value. Figure 4-26 illustrates the generation of a single pulse with a pulse delay of two and a pulse-width of four. Figure 4-26: Mode 4 Operation Mode 5: Single Triggered Pulse Generation This function generates a single pulse with programmable delay and pro-grammable pulse-width following an active GPTC_GATE edge.
Mode 6: Re-triggered Single Pulse Generation This mode is similar to mode5 except that the counter generates a pulse following every active edge of GPTC_GATE. After the software-start, every active GPTC_GATE edge triggers a single pulse with programmable delay and pulse-width. Any GPTC_GATE triggers that occur when the prior pulse is not completed would be ignored. Figure 4-28 illustrates the generation of two pulses with a pulse delay of two and a pulse-width of four.
Mode 8: Continuous Gated Pulse Generation This mode generates periodic pulses with programmable pulse interval and pulse-width following the software-start. GPTC_GATE is used to enable/disable counting. When GPTC_GATE is inactive, the counter halts the current count value. Figure 4-30 illustrates the generation of two pulses with a pulse delay of four and a pulse-width of three. Figure 4-30: Mode 8 Operation 4.5 Trigger Sources We provide flexible trigger selections in the DAQ/PXI-20XXseries products.
level for SRC1 is ±10V and the resolution is 78mV (please refer to Table 4-6), while the trigger range of SRC2 is the full-scale range of the selected channel input, and the resolution is the desired range divided by 256. For example, if the channel input selected to be the trigger source is set bipolar and ±5V range, the trigger voltage would be 4.96V when the trigger level code is set to 0xFF while 0V when the code is set to 0x80.
Below-Low analog trigger condition Figure 4-32 shows the below-low analog trigger condition, the trigger signal is generated when the input analog signal is less than the Low_Threshold voltage, and the High_Threshold setting is not used in this trigger condi-tion.
should be always higher then the Low_Threshold voltage setting. Figure 4-34: Inside-Region analog trigger condition High-Hysteresis analog trigger condition Figure 4-35 shows the high-hysteresis analog trigger condition, the trigger signal is generated when the input analog signal level is greater than the High_Threshold voltage, and the Low_Threshold voltage determines the hysteresis duration. Note the High_Threshold setting should be always higher then the Low_Threshold voltage setting.
High_Threshold voltage determines the hysteresis duration. Note the High_Threshold setting should be always higher then the Low_Threshold voltage setting. Figure 4-36: Low-Hysteresis analog trigger condition External Digital Trigger An external digital trigger occurs when a rising edge or a falling edge is detected on the digital signal connected to the EXTDTRIG or the EXTWFTRG of the 68-pin connector for external digital trigger.
20XX series provides flexible user-controllable timing signals to connect to external circuitry or additional cards. The whole DAQ timing of the DAQ/PXI-20XX series is composed of a bunch of counters and trigger signals in the FPGA. These timing signals are related to the A/D, D/A conversions and Timer/ Counter applications. These timing signals can be inputs to or outputs from the I/O connectors, the SSI connector and the PXI bus.
Timing signal category Corresponding functionality AFI signals Control DAQ-2000 by external timing signals AI_Trig_Out, AO_Trig_Out Control external circuitry or boards Table 4-8: Summary of user-controllable timing signals and the corresponding functionalities DAQ timing signals The user-controllable internal timing-signals contain: (Please refer to Section 4.1 for the internal timing signal definition) 1.
should be TTL-compatible and the minimum pulse width is 20ns. 5. DA_TRIG, the trigger signal for the D/A operation, which could be derived from external digital trigger, analog trigger, internal software trigger and SSI_AD_TRIG. Refer to Section 4.5 for detailed de-scription. 6. DAWR, the update signal to initiate a single D/A conversion, which could be derived from internal counter, AFI[1] or SSI_DAWR. Note that this signal is edge-sensitive.
Category Dedicated input Timing signal Functionality EXTTIMEBASE Replace the internal TIMEBASE Constraints 1. TTL-compatible 2. 1MHz to 40MHz 3. Affects on both A/D and D/A operations EXTDTRIG 1. TTL-compatible External digi2. Minimum pulse tal trigger width = 20ns input for A/D 3. Rising edge or falloperation ing edge EXTWFTRG 1. TTL-compatible External digi2. Minimum pulse tal trigger width = 20ns input for D/A 3. Rising edge or falloperation ing edge 1.
EXTTIMEBASE When the applications needs specific sampling frequency or update rate that the card could not generate from its internal TIMEBASE, the 40MHz clock, users could utilize the EXTTIMEBASE with internal counters to achieve the specific timing intervals for both A/D and D/A operations. Note that once you choose the TIMEBASE source, both A/D and D/A operations will be affected because A/D and D/A operations share the same TIMEBASE.
AFI[1]. Note that the AFI[1] is a multi-purpose input, and it can only be utilized for one function at any one time. AFI[1] currently only has one function. ADLINK reserves it for future development. System Synchronization Interface SSI (System Synchronization Interface) provides the DAQ timing syn-chronization between multiple cards.
In PCI form factor, there is a connector on the top right corner of the card for the SSI. Refer to section 2.3 for the connector position. All the SSI signals are routed to the 20-pin connector from the FPGA. To synchronize multiple cards, users can connect a special ribbon cable (ACL-SSI) to all the cards in a daisy-chain configuration In PXI form factor, we utilize the PXI trigger bus built on the PXI backplane to provide the necessary timing signal connections.
For example: We want to synchronize the A/D operation through the ADCONV signal for 4 DAQ/PXI-20XX cards. Card 1 is the master, and Card 2, 3, 4 are slaves. Card 1 receives an external digital trigger to start the post trigger mode acquisition. The SSI setting could be: 1. Set the SSI_ADCONV signal of Card 1 to be the master. 2. Set the SSI_ADCONV signals of Card 2, 3, 4 to be the slaves. 3. Set external digital trigger for Card 1’s A/D operation. 4.
VHDCI). Connecting them to any signal source may cause per-manent damage.
5 Calibration This chapter introduces the calibration process to minimize AD meas-urement errors and DA output errors. 5.1 Loading Calibration Constants The DAQ/PXI-20XX is factory calibrated before shipment by writing the associated calibration constants of TrimDACs to the onboard EEPROM. TrimDACs are devices containing multiple DACs within a single package. TrimDACs do not have memory capability. That means the calibration constants do not retain their values after the system power is turned off.
recommended for users to adjust the on-board calibration reference except when an ultra-precision cali-brator is available. Note: 1. Before auto-calibration procedure starts, it is recommended to warn up the card for at least 15 minutes. 2. Please remove the cable before an auto-calibration procedure is initiated because the DA outputs would be changed in the process of calibration. 5.
Warranty Policy Thank you for choosing ADLINK. To understand your rights and enjoy all the after-sales services we offer, please read the following carefully. 1. Before using ADLINK’s products please read the user manual and follow the instructions exactly. When sending in damaged products for repair, please attach an RMA application form which can be downloaded from: http:// rma.adlinktech.com/policy/. 2.
3. Our repair service is not covered by ADLINK's guarantee in the following situations: X Damage caused by not following instructions in the User's Manual. X Damage caused by carelessness on the user's part during product transportation. X Damage caused by fire, earthquakes, floods, lightening, pollution, other acts of God, and/or incorrect usage of voltage transformers. X Damage caused by unsuitable storage environments (i.e. high temperatures, high humidity, or volatile chemicals).
