DAQ-/DAQe-/PXI2204/2205/2206/2208 64-/96-CH High Performance Multi-Function Data Acquisition Card User’s Manual Manual Rev. 2.01 Revision Date: December 04, 2007 Part No: 50-11220-2010 Advance Technologies; Automate the World.
Copyright 2007 ADLINK TECHNOLOGY INC. All Rights Reserved. The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer. In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.
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Using this manual 1.1 Audience and scope This manual guides you when using ADLINK multi-function DAQ-/ DAQe-/PXI-2204/2205/2206/2208 card. The card’s hardware, signal connections, and calibration information are provided for faster application building. This manual is intended for computer programmers and hardware engineers with advanced knowledge of data acquisition and high-level programming. 1.
1.3 Conventions Take note of the following conventions used throughout the manual to make sure that you perform certain tasks and instructions properly. NOTE Additional information, aids, and tips that help you perform particular tasks. IMPORTANT Critical information and instructions that you MUST perform to complete a task. WARNING Information that prevents physical injury, data loss, module damage, program corruption etc. when trying to complete a particular task.
Table of Contents Table of Contents..................................................................... i List of Tables.......................................................................... iii List of Figures ........................................................................ iv 1 Introduction ........................................................................ 1 1.1 1.2 1.3 1.4 Features............................................................................... 2 Applications ..........
4.1 4.2 4.3 4.4 4.5 4.6 A/D Conversion.................................................................. 33 DAQ-/DAQe-/PXI-2204/2208 AI Data Format .............. 33 DAQ/DAQe/PXI-2005/2006/2016 AI Data Format ........ 36 Software Conversion with Polling Data Transfer Acquisition Mode (Software Polling) .... 37 Programmable Scan Acquisition Mode ......................... 38 Specifying Channels, Gains, and Input Configurations in the Channel Gain Queue ........ 40 Trigger Modes ............................
List of Tables Table 1-1: Table 1-2: Table 1-3: Table 1-4: Table 1-5: Table 3-1: Table 3-2: Table 3-3: Table Table Table Table Table 3-4: 3-5: 3-6: 3-7: 4-1: Table 4-2: Table 4-3: Table 4-4: Table 4-5: Table 4-6: Table 4-7: Table 4-8: Table 4-9: Table 4-10: List of Tables Programmabel Input Range ..................................... 4 Bandwidth ................................................................. 5 System Noise ...........................................................
List of Figures Figure 2-1: Figure 2-2: Figure 2-3: Figure 3-1: Figure 3-2: DAQe-2204/2205/2206/2208 Card Layout .............. DAQ-2204/2205/2206/2208 Card Layout ................ PXI-2204/2205/2206/2208 Card Layout .................. Floating Source and RSE Input Connections .......... Ground-referenced Sources and NRSE nput Connections..................................................... Figure 3-3: Ground-referenced Source and Differential Input.... Figure 3-4: Floating Source and Differential Input ..
Figure 4-26: Mode4 Operation..................................................... Figure 4-27: Mode5 Operation..................................................... Figure 4-28: Mode6 Operation..................................................... Figure 4-29: Mode7 Operation..................................................... Figure 4-30: Mode8 Operation..................................................... Figure 4-31: Analog Trigger Block Diagram.................................
vi List of Figures
1 Introduction The DAQ-/DAQe-/PXI-2204/2205/2206/2208 card is an advanced data acquisition card based on the 32-bit PCI or PCI Express® architecture. High performance designs and state-of-the-art technology make these cards ideal for data logging and signal analysis applications in medical, process control, etc.
1.
1.2 Applications X Automotive Testing X Cable Testing X Transient signal measurement X ATE X Laboratory Automation X Biotech measurement 1.
X Programmable input range: Device Bipolar input range 2204/ 2208 2205/ 2206 Unipolar input range ±10 V — ±5 V 0 to 10 V ±2.5 V 0 to 5 V ±2 V 0 to 4 V ±1.25 V 0 to 2.5 V ±1 V 0 to 2 V ±0.5 V 0 to 1 V ±0.25 V 0 to 0.5 V ±0.2 V 0 to 0.4 V ±0.05 V 0 to 0.1 V ±10 V 0 to 10 V ±5 V 0 to 5 V ±2.5 V 0 to 2.5 V ±1.25 V 0 to 1.
X Bandwidth (Typical 25ºC): Device 2204/ 2208 2205 2206 Input range ±10 V — ±5 V 0 V to 10 V ±2.5 V 0 V to 5 V ±1.25 V 0 V to 2.5 V ±2 V 0 V to 4 V ±0.5 V 0 V to 1 V ±1 V 0 V to 2 V ±0.25 V 0 V to 0.5 V ±0.2 V 0 V to 0.4 V ±0.05 V 0 V to 0.1 V ±10 V 0 V to 0 V Small signal bandwidth (-3dB) Large signal bandwidth (1% THD) 2000 kHz — 1450 kHz — 990 kHz — 240 kHz — 1600 kHz 300 kHz ±5 V 0 V to 5 V 1400 kHz 310 kHz ±2.5 V 0 V to 2.5 V 1000 kHz 310 kHz ±1.
X System Noise (LSBrms, including Quantization, Typical, 25°C) Device 2205 2206 Input Range System Noise Input Range System Noise ±10 V 0.95 LSBrms 0 V to 10 V 1.5 LSBrms ±5 V 1.0 LSBrms 0 V to 5 V 1.6 LSBrms ±2.5 V 1.1 LSBrms 0 V to 2.5 V 1.7 LSBrms ±1.25 V 1.3 LSBrms 0 V to 1.25 V 1.9 LSBrms ±10 V 0.8 LSBrms 0 V to 10 V 0.9 LSBrms ±5 V 0.85 LSBrms 0 V to 5 V 1.0 LSBrms ±2.5 V 0.85 LSBrms 0 V to 2.5 V 1.0 LSBrms ±1.25 V 0.9 LSBrms 0 V to 1.25 V 1.
X Settling time to full-scale step (Typical, 25°C): Device Input Range Condition Settling time ±10 V • Multiple channels, multiple ranges. • All samples in unipolar/ bipolar mode. 1 µs to 0.1% error ±5 V 0 to 10 V ±2.5 V 0 to 5 V ±2 V 0 to 4 V ±1.25 V 0 to 2.5 V ±0.5 V 0 to 1 V ±10 V 2204/ 2208 ±5 V 0 to 10 V ±2.5 V 0 to 5 V v2 V 0 to 4 V ±1.25 V 0 to 2.5 V ±0.5 V 0 to 1 V • Multiple channels, multiple ranges. • All samples in unipolar/ bipolar mode. 1.25 µs to 0.
X Time-base source: Z Internal 40 MHz or external clock Input (fmax: 40 MHz, fmin: 1 MHz, 50% duty cycle) X Trigger modes: Post-trigger, delay-trigger, pre-trigger and middle-trigger X Offset error: X Z Before calibration: ±60 mV max Z After calibration: ±1 mV max Gain error (relative to calibration reference): Z Before calibration: 0.6% of reading Z After calibration (gain = 1): 0.03% of reading max for DAQ-/DAQe-/PXI-2204/2208 0.
Analog Output (AO) NOTE X X X X X X The DAQ-/DAQe-/PXI-2208 card does not support this function.
General Purpose Digital I/O (G.P. DIO, 82C55A) X Channels: 24 programmable input/output X Compatibility: TTL X Input voltage: X X Z Logic Low: VIL=0.8 V max; IIL=0.2 mA max Z High: VIH=2.0 V max; IIH=0.02 mA max Output voltage: Z Low: VOL=0.5 V max; IOL=8 mA max Z High: VOH=2.7 V min; IOH=400 µA Synchronous Digital Inputs (SDI): On DAQ-/DAQe-/PXI2204 model only.
Analog Trigger (A.Trig) X Source: Z All analog input channels Z External analog trigger (EXTATRIG) X Level: ±Full-scale, internal; ±10 V external X Resolution: 8-bit X Slope: Positive or negative (software-selectable) X Hysteresis: Programmable X Bandwidth: 400 kHz External Analog Trigger Input (EXTATRIG) X Input Impedance: Z 40 kΩ for DAQ-/DAQe-/PXI-2204/2208 Z 20 kΩ for DAQ-/DAQe-/PXI-2205/2206 X Coupling: DC X Protection: Continuous ±35 V maximum Digital Trigger (D.
Physical X X Dimensions: Z 175mm by 107mm for DAQ-/DAQe-2204/2205/2206/ 2208 Z Standard CompactPCI form factor for PXI-2204/2205/ 2206/2208 I/O connector: 68-pin female VHDCI type (e.g. AMP787254-1) Power Requirement (typical) X X X +5 VDC Z 1.3 A for DAQ-/DAQe-/PXI-2204 Z 1.2 A for DAQ-/DAQe-/PXI-2205/2206 Z 950 mA for DAQ-/DAQe-/PXI-2208 +12 VDC Z 358 mA for DAQe-2204 Z 344 mA for DAQe-2205 Z 390 mA for DAQe-2206 Z 258 mA for DAQe-2208 +3.
1.4 Software Support ADLINK provides versatile software drivers and packages for users’ different approach to building up a system. ADLINK not only provides programming libraries such as DLL for most Windowsbased systems, but also provide drivers for other software packages such as LabVIEW®. All software options are included in the ADLINK CD. Non-free software drivers are protected with licensing codes.
DAQ-LVIEW PnP: LabVIEW Driver DAQ-LVIEW PnP contains the VIs, which are used to interface with NI’s LabVIEW software package. The DAQ-LVIEW PnP supports Windows 98/NT/2000/XP. The LabVIEW drivers is shipped free with the card. You can install and use them without a license. For detailed information about DAQ-LVIEW PnP, refer to the user’s guide in the CD.
2 Installation This chapter describes how to install the DAQ-/DAQe-/PXI-2204/ 2205/2206/2208 card. The contents of the package and unpacking information that you should be aware of are outlined first. The DAQ-/DAQe-/PXI-2204/2205/2206/2208 card performs an automatic configuration of the IRQ and port address. You can use the PCI_SCAN software utility to read the system configuration. 2.
Again, inspect the module for damages. Press down on all the socketed IC's to make sure that they are properly seated. Do this only with the module place on a firm flat surface. You are now ready to install your DAQ-/DAQe-/PXI-2204/2205/ 2206/2208 card. NOTE 16 DO NOT APPLY POWER TO THE CARD IF IT HAS BEEN DAMAGED.
2.
DAQ-2204/2205/2206/2208 Figure 2-2: DAQ-2204/2205/2206/2208 Card Layout PXI-2204/2205/2206/2208 Figure 2-3: PXI-2204/2205/2206/2208 Card Layout 18 Installation
2.4 PCI Configuration Plug and Play With support for plug and play, the card requests an interrupt number via its PCI controller. The system BIOS responds with an interrupt assignment based on the card information and on known system parameters. These system parameters are determined by the installed drivers and the hardware load seen by the system. Configuration The board configuration is done on a board-by-board basis for all PCI boards in the system.
20 Installation
3 Signal Connections This chapter describes DAQ-/DAQe-/PXI-2204/2205/2206/2208 card connectors and the signal connection between the DAQ-/ DAQe-/PXI-2204/2205/2206/2208 card and external devices. 3.1 Connectors Pin Assignment The DAQ-/DAQe-/PXI-2204/2205/2206/2208 card is equipped with two 68-pin VHDCI-type connector (AMP-787254-1). It is used for digital input/output, analog input/output, timer/counter signals, etc.
CN1 Connector AI0 (AIH0) AI1 (AIH1) AI2 (AIH2) AI3 (AIH3) AI4 (AIH4) AI5 (AIH5) AI6 (AIH6) AI7 (AIH7) AI8 (AIH8) AI9 (AIH9) AI10 (AIH10) AI11 (AIH11) AI12 (AIH12) AI13 (AIH13) AI14 (AIH14) AI15 (AIH15) AISENSE AI16 (AIH16) AI17 (AIH17) AI18 (AIH18) AI19 (AIH19) AI20 (AIH20) AI21 (AIH21) AI22 (AIH22) AI23 (AIH23) AI24 (AIH24) AI25 (AIH25) AI26 (AIH26) AI27 (AIH27) AI28 (AIH28) AI29 (AIH29) AI30 (AIH30) AI31 (AIH31) EXTATRIG 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
AI0 (AIH0) AI1 (AIH1) AI2 (AIH2) AI3 (AIH3) AI4 (AIH4) AI5 (AIH5) AI6 (AIH6) AI7 (AIH7) AISENSE AI8 (AIH8) AI9 (AIH9) AI10 (AIH10) AI11 (AIH11) AI12 (AIH12) AI13 (AIH13) AI14 (AIH14) AI15 (AIH15) AI16 (AIH16) AI17 (AIH17) AI18 (AIH18) AI19 (AIH19) AI20 (AIH20) AI21 (AIH21) AI22 (AIH22) AI23 (AIH23) AIGND AI24 (AIH24) AI25 (AIH25) AI26 (AIH26) AI27 (AIH27) AI28 (AIH28) AI29 (AIH29) AI30 (AIH30) AI31 (AIH31) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 3
CN2 Connector DA0OUT DA1OUT AOEXTREF NC DGND EXTWFTRIG EXTDTRIG SSHOUT RESERVED RESERVED AFI1 AFI0 GPTC0_SRC GPTC0_GATE GPTC0_UPDOWN GPTC0_OUT GPTC1_SRC GPTC1_GATE GPTC1_UPDOWN GPTC1_OUT EXTTIMEBASE PB7 PB5 PB3 PB1 PC7 PC5 DGND PC3 PC1 PA7 PA5 PA3 PA1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 AOGND AOGND AOGND NC DGND DGND DGND SDI0 / DGND* SDI1 / DGND*
AI32 (AIH32) AI33 (AIH33) AI34 (AIH34) AI35 (AIH35) AI36 (AIH36) AI37 (AIH37) AI38 (AIH38) AI39 (AIH39) EXTATRIG AI40 (AIH40) AI41 (AIH41) AI42 (AIH42) AI43 (AIH43) AI44 (AIH44) AI45 (AIH45) AI46 (AIH46) AI47 (AIH47) AIGND NC EXTDTRIG EXTTIMEBASE PB7 PB5 PB3 PB1 PC7 PC5 DGND PC3 PC1 PA7 PA5 PA3 PA1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 (AIL32) AI80 (
CN1/CN2 Connector Signal Description Signal Name AIGND AI<0..63/95> AISENSE Reference Direction — AIGND AIGND — Input Input Analog Input Sense. This pin is the reference for any channels AI<0..63> in NRSE input configuration. External AI analog trigger AIGND Input DA0OUT AOGND Output DA1OUT AOGND Output AOGND Analog ground for AI. All three ground references (AIGND, AOGND, and DGND) are connected together on board. • For DAQ-/DAQe-/PXI-2204/ 2205/2206: Analog Input Channels 0~63.
Signal Name Reference Direction Description SDI<0..3> (for 2204 only) DGND Input Synchronous digital inputs. These 4 digital inputs are sampled simultaneously with the analog signal input.
SSI Connector SSI_TIMEBASE 1 2 DGND SSI_ADCONV 3 4 DGND SSI_DAWR / RESERVED* 5 6 DGND SSI_SCAN_START 7 8 DGND RESERVED 9 10 DGND SSI_AD_TRIG 11 12 DGND SSI_DA_TRIG / RESERVED* 13 14 DGND RESERVED 15 16 DGND RESERVED 17 18 DGND RESERVED 19 20 DGND Table 3-6: SSI Connector Pin Assignment *Pin 5 and 13 are reserved for DAQ/PXI-2208.
3.2 Analog Input Signal Connection The DAQ-/DAQe-/PXI-2204/2205/2206/2208 card provides up to 64 single-ended or 32 differential analog input channels. You can fill the Channel Gain Queue to get desired combination of the input signal types. The analog signal can be converted to digital values by the A/D converter. To avoid ground loops and get more accurate measurements from the A/D conversion, it is important to understand the signal source type and how to connect the analog input signals.
Referenced Single-ended (RSE) Mode In referenced single-ended mode, all input signals are connected to the ground provided by the DAQ-/DAQe-/PXI-2204/ 2205/2206/2208 card. This is suitable for connections with floating signal sources. Figure 3-1 shows an illustration. Note that when more than two floating sources are connected, these sources will be referenced to the same common ground.
Differential Input Mode The differential input mode provides two inputs that respond to signal voltage difference between them. If the signal source is ground-referenced, the differential mode can be used for the common-mode noise rejection. Figure 3-3 shows the connection of ground-referenced signal sources under differential input mode. x = 0, ...
32 Signal Connections
4 Operation Theory The operation theory of the DAQ-/DAQe-/PXI-2204/2205/2206/ 2208 card functions are described in this chapter. The functions include the A/D conversion, D/A conversion, digital I/O, and general purpose counter/timer. The operation theory can help you understand how to configure and program the DAQ-/DAQe-/PXI2204/2205/2206/2208 card. 4.1 A/D Conversion When using an A/D converter, you must know about the properties of the signal to be measured.
SDI<3..0> SDI<3..0> from CN2 16-bit Register 4 From Instrumentation Amplifier ADC Ain 16 12 nADBUSY AD_conversion AD<11..0> nADBUSY AD Data FIFO CLK nADCONV Figure 4-1: Synchronous Digital Inputs Block Diagram AD_conversion nADBUSY 16 bits data(including AD<11..0> and SDI<3..0> latched into AD Data FIFO Figure 4-2: Synchronous Digital Inputs Timing NOTE 34 Since the analog signal is sampled when an A/D conversion starts (falling edge of A/D_conversion signal), while SDI<3..
Table 4-1and Table 4-2 illustrate the ideal transfer characteristics of various input ranges of the DAQ-/DAQe-/PXI-2204/2205/2206/ 2208 card. Description Full-scale Range Digital code Bipolar Analog Input Range ±10V ±5V ±2.5V ±1.25V — Least significant bit 4.88mV 2.44mV 1.22mV 0.61mV — FSR-1LSB 9.9951V 4.9976V 2.4988V 1.2494V 7FFX Midscale +1LSB 4.88mV 2.44mV 1.22mV 0.61mV 001X Midscale 0V 0V 0V 0V 000X Midscale –1LSB -4.88mV -2.44mV -1.22mV -0.
DAQ/DAQe/PXI-2005/2006/2016 AI Data Format The data format of the acquired 16-bit A/D data is 2's Complement coding. Table 4-3 and Table 4-4 illustrate the valid input ranges and the ideal transfer characteristics. Description Digital code Bipolar Analog Input Range Full-scale Range ±10V ±5V ±2.5V ±1.25V — Least significant bit 305.2 µV 152.6 µV 76.3 µV 38.15 µV — FSR-1LSB Midscale +1LSB 9.999695V 4.999847V 2.499924V 1.249962V 305.2 µV 152.6 µV 76.3 µV 38.
Software Conversion with Polling Data Transfer Acquisition Mode (Software Polling) This is the easiest way to acquire a single A/D data. The A/D converter starts one conversion whenever the dedicated software command is executed. Then the software would poll the conversion status and read the A/D data back when it is available. This method is very suitable for applications that needs to process A/D data in real time. Under this mode, the timing of the A/D conversion is fully controlled by the software.
Programmable Scan Acquisition Mode Scan Timing and Procedure It is recommended that you use this mode if your applications need a fixed and precise A/D sampling rate. You can accurately program the period between conversions of individual channels.
3 Scans, 4 Samples per scan (PSC_Counter=3, NumChan_Counter=4) ( channel sequences are specified in Channel Gain Queue) Ch2 Ch3 Ch1 Ch0 Ch2 Ch3 Ch1 Ch0 Ch2 Ch3 Ch1 Ch0 Scan_start AD_conversion Scan_in_progress (SSHOUT)(pin8 on CN2) Acquisition_in_progress Sampling Interval t= SI2_COUNTER/TimeBase Scan Interval T= SI_COUNTER/TimeBase Figure 4-3: Scan Timing There are four trigger modes to start the scan acquisition. Refer to section 4.1 for details.
Scan with SSH You can send the SSHOUT signal on CN2 to external S&H circuits to sample and hold all signals if you want to simultaneously sample all channels in a scan, as illustrated in Figure 4-3. NOTES The DAQ-/DAQe-/PXI-2208 does not support this function. The SSHOUT signal is sent to external S&H circuits to hold the analog signal. You must implement external S&H circuits on their own to carry out the S&H function. There are no onboard S&H circuits.
Then X Acquisition sequence of channels: 1, 2, 0, 2, 1, 2, 0, 2, 1, 2, 0, 2 X Sampling interval: 160/40 Ms = 4 µs X Scan interval: 640/40 Ms = 16 µs X Equivalent sampling rate of ch0, ch1: 62.
Trigger Modes The DAQ-/DAQe-/PXI-2204/2205/2206/2208 card provides four trigger sources (internal software trigger, external analog trigger, and digital trigger sources, and SSI trigger signals). You must select one of them as the source of the trigger event. A trigger event occurs when the specified condition is detected on the selected trigger source. For example, a rising edge on the external digital trigger input. Refer to section 4.6 for more information on SSI signals.
Pre-Trigger Acquisition Use pre-trigger acquisition in applications where you want to collect data before a trigger event. The A/D starts to sample when you execute the specified function calls to begin the pretrigger operation, and it stops when the trigger event occurs. Users must program the value M in M_counter (16 bits) to specify the amount of the stored scans before the trigger event.
Note that if a trigger event occurs when a scan is in progress, the data acquisition won't stop until the scan completes, and the stored M scans of data includes the last scan.
When the trigger signal occurs before the first M scans of data are converted, the amount of stored data could be fewer than the originally specified amount M_counter, as illustrated in Figure 4-6. This situation can be avoided by setting M_enable. If M_enable is set to 1, the trigger signal will be ignored until the first M scans of data are converted, and it assures the user M scans of data under pre-trigger mode, as illustrated in Figure 4-7.
(M_counter = M = 3, NumChan_counter=4, PSC_counter=0) The first M scans Trigger signals which occur in the shadow region(the first M scans) will be ignored Trigger Scan_start AD_conversion Scan_in_progress (SSHOUT)(pin2 on CN2) Acquisition_in_progress Aquired data Acquired & stored data (M scans) Operation start Figure 4-7: Pre-trigger with M_enable=1 NOTE 46 The PSC_counter is set to 0 in pre-trigger acquisition mode.
Middle-Trigger Acquisition Use middle-trigger acquisition in applications where you want to collect data before and after a trigger event. The number of scans (M) stored before the trigger is specified in M_counter, while the number of scans (N) after the trigger is specified in PSC_counter. Like pre-trigger mode, the number of stored data could be less than the specified amount of data (M+N), if an external trigger occurs before M scans of data are converted.
If the trigger event occurs when a scan is in progress, the stored N scans of data would include this scan, as illustrated in Figure 4-9.
Post-Trigger Acquisition Use post-trigger acquisition in applications where you want to collect data after a trigger event. The number of scans after the trigger is specified in PSC_counter, as illustrated in Figure 410. The total acquired data length = NumChan_counter * PSC_counter.
Delay Trigger Acquisition Use delay trigger acquisition in applications where you want to delay the data collection after the occurrence of a specified trigger event. The delay time is controlled by the value, which is pre-loaded in the Delay_counter (16-bit). The counter counts down on the rising edge of the Delay_counter clock source after the trigger condition is met. The clock source can be software-programmed either by the TIMEBASE clock (40 MHz) or A/D sampling clock (TIMEBASE / SI2_counter).
Post-Trigger or Delay-trigger Acquisition with re-trigger Use post-trigger or delay-trigger acquisition with re-trigger function in applications where you want to collect data after several trigger events. The number of scans after each trigger is specified in PSC_counter, and users could program Retrig_no to specify the re-trigger numbers. Figure 4-12 illustrates an example.
Bus-mastering DMA Data Transfer PCI bus-mastering DMA is necessary for high speed DAQ in order to utilize the maximum PCI bandwidth. The bus-mastering controller, which is built in the PLX IOP-480 PCI controller, controls the PCI bus when it becomes the master of the bus. Bus mastering reduces the size of the on-board memory and reduces the CPU loading because data is directly transferred to the computer’s memory without host CPU intervention.
Figure 4-13 shows a linked list that is constructed by three DMA descriptors. Each descriptor contains a PCI address, a local address, a transfer size, and the pointer to the next descriptor. You can allocate many small size memory blocks and chain their associative DMA descriptors altogether by their application programs. The DAQ-/DAQe-/PXI-2204/2205/2206/2208 card software driver provides simple settings for the scatter/gather function, including some sample programs in the ADLINK All-inOne CD.
4.2 D/A Conversion NOTE The DAQ-/DAQe-/PXI-2208 card does not support this function. There are two 12-bit D/A output channels available in the DAQ-/ DAQe-/PXI-2204/2205/2206 card. When using D/A converters, you should assign and control the D/A converter reference sources for the D/A operation mode and D/A channels. You could also set the output polarity to unipolar or bipolar. The reference selection control lets you utilize in full the multiplying characteristics of the D/A converters.
Digital Code Analog Output 111111111111 Vref * (4095/4096) 100000000000 Vref * (2048/4096) 000000000001 Vref * (1/4096) 000000000000 0V Table 4-6: Unipolar Output Code Table The D/A conversion is initiated by a trigger source. You must decide how to trigger the D/A conversion. The data output will start when a trigger condition is met. Before the start of D/A conversion, D/A data is transferred from the computer’s main memory to a buffering Data FIFO.
Timed Waveform Generation This mode can provide your applications with a precise D/A output with a fixed update rate. It can be used to generate an infinite or finite waveform. You can accurately program the update period of the D/A converters. The D/A output timing is provided through a combination of counters in the FPGA on board. There are a total of five counters to be specified.
4 update counts, 3 iterations (UC _Counter=4, IC_Counter=3) Trigger UC_Counter=4 DAWR WFG_in_progress Delay until DLY1_Counter reaches 0 Delay until DLY2_Counter reaches 0 Delay until DLY2_Counter reaches 0 DA update_interval t= UI_Counter/Timebase 4 2 Output Waveform 0 -4 Operation start A single waveform IC_Counter = 3 Figure 4-14: Typical D/A Timing of Waveform Generation NOTE The maximum D/A update rate is 1 MHz.
Trigger Modes Post-Trigger Generation Use post-trigger when you want to perform DA waveform right after a trigger event occurs. In this trigger mode DLY1_Counter is ignored and not be specified. Figure 4-15 shows a single waveform generated right after a trigger signal is detected and assuming the data in the data buffer are 2V, 4V, 6V, 3V, 0V, 4V, -2V, and 4V. The trigger signal could come from a software command, an analog trigger or a digital trigger. Refer to section 4.5 for detailed information.
Figure 4-16: Delay Trigger Waveform Generation Post-Trigger or Delay-Trigger with Re-trigger Use post-trigger or delay-trigger with re-trigger function when you want to generate waveform after more than one trigger events. The re-trigger function can be enabled or disabled by software setting. In Figure 4-17, each trigger signal will initiate a waveform generation assuming the data in the data buffer are 2V, 4V, 2V, and 0V.
Iterative Waveform Generation Set IC_Counter in order to generate iterative waveforms from the data of a single waveform. The counter stores the iteration number and the iterations may be finite (Figure 4-18) or infinite (Figure 4-19). Take note that in infinite mode the waveform generation does not stop until software stop function is executed and IC_Counter is still valid when stop mode III is selected. Both figures assume that the data in the data buffer are 2V, 4V, 2V, and 0V.
Figure 4-19: Infinite Iterative Waveform Generation with Post-trigger (DLY2_Counter = 0) Delay2 in Iterative Waveform Generation To stretch out the flexibility of the D/A waveform generation, we add a DLY2_Counter to separate two consecutive waveforms in iterative waveform generation. The time between two waveforms is assigned by setting the value of the DLY2_Counter.
Stop Modes of Scan Update You can call software stop function to stop waveform generation when it is still in progress. Three stop modes are provided for timed waveform generation meant to stop the waveform generation. You can apply these three modes to stop waveform generation no matter infinite or finite waveform generation mode is selected. Figure 4-20 illustrates an example for stop mode I, assuming the data in the data buffer are 2V, 4V, 2V, and 0V.
In stop mode II, after a software stop command is given, the waveform generation does not stop until a complete single waveform is finished. See Figure 4-21. Since the UC_counter is set to four, the total DA update counts (number of pulses of DAWR signal) must be a multiple of four (update counts = 20 in this example).
4.3 Digital I/O The DAQ-/DAQe-/PXI-2204/2205/2206/2208 card contains 24 lines of general-purpose digital I/O (GPIO) which is provided through the 82C55A chip. The 24-line GPIO are separated into three ports: Port A, Port B and Port C. Port A and Port B can be programmed to be either input or output ports. Port C can be separated into high bit (PC4PC7) and low bit (PC0-PC3), and both high bit and low bit ports can be programmed for input or output.
The Basics of Timer/Counter Functions Each timer/counter has three inputs that can be controlled via hardware or software. These are clock input (GPTC_CLK), gate input (GPTC_GATE), and up/down control input (GPTC_UPDOWN). The GPTC_CLK input provides a clock source input to the timer/counter. Active edges on the GPTC_CLK input make the counter increment or decrement. The GPTC_UPDOWN input controls whether the counter counts up or down.
Mode1: Simple Gated-Event Counting In this mode, the counter counts the number of pulses on the GPTC_CLK after the software-start. Initial count can be loaded from software. Current count value can be read-back by software any time without affecting the counting. GPTC_GATE is used to enable/disable counting. When GPTC_GATE is inactive, the counter halts the current count value. Figure 4-23 illustrates the operation with initial count = 5, countdown mode.
Figure 4-24: Mode2 Operation Mode3: Single Pulse-width Measurement In this mode, the counter counts the pulse-width of the signal on GPTC_GATE in terms of GPTC_CLK. Initial count can be loaded from software. After the software-start, the counter counts the number of active edges on GPTC_CLK when GPTC_GATE is in its active state. After the completion of the pulse-width interval on GPTC_GATE, GPTC_OUT outputs high, then current count value can be read-back by software.
Mode4: Single Gated Pulse Generation This mode generates a single pulse with programmable delay and programmable pulse-width following the software-start. The two programmable parameters could be specified in terms of periods of the GPTC_CLK input by software. GPTC_GATE is used to enable/disable counting. When GPTC_GATE is inactive, the counter halts the current count value. Figure 4-26 illustrates the generation of a single pulse with a pulse delay of two and a pulse-width of four.
Figure 4-27: Mode5 Operation Mode6: Re-triggered Single Pulse Generation This mode is similar to Mode5 except that the counter generates a pulse following every active edge of GPTC_GATE. After the software-start, every active GPTC_GATE edge triggers a single pulse with programmable delay and pulse-width. Any GPTC_GATE triggers that occur when the prior pulse is not completed would be ignored. Figure 4-28 illustrates the generation of two pulses with a pulse delay of two and a pulse-width of four.
Mode7: Single Triggered Continuous Pulse Generation This mode is similar to Mode5 except that the counter generates continuous periodic pulses with programmable pulse interval and pulse-width following the first active edge of GPTC_GATE. Once the first GPTC_GATE edge triggers the counter, GPTC_GATE takes no effect until the software-start is re-executed. Figure 4-29 illustrates the generation of two pulses with a pulse delay of four and a pulse-width of three.
4.5 Trigger Sources ADLINK provides flexible trigger selections in the DAQ-/DAQe-/ PXI-2204/2205/2206/2208 card. In addition to the internal software trigger, the DAQ-/DAQe-/PXI-2204/2205/2206/2208 card also supports external analog, digital triggers, and SSI triggers. You can configure the trigger source by software for A/D and D/A processes individually. Note that the A/D and the D/A conversion share the same analog trigger. Software-Trigger This trigger mode does not need any external trigger source.
Figure 4-31: Analog Trigger Block Diagram Trigger level digital setting Trigger voltage 0xFF 9.92V 0xFE 9.84V 0x81 0.08V 0x80 0 0x7F -0.08V 0x01 -9.92V Table 4-7: Analog Trigger SRC1 (EXTATRIG) Ideal Transfer Characteristic The trigger signal is generated when the analog trigger condition is satisfied. There are five analog trigger conditions in the DAQ-/ DAQe-/PXI-2204/2205/2206/2208 card.
Below-Low Analog Trigger Condition Figure 4-32 shows the below-low analog trigger condition, the trigger signal is generated when the input analog signal is less than the Low_Threshold voltage, and the High_Threshold setting is not used in this trigger condition.
Inside-Region Analog Trigger Condition Figure 4-34 shows the inside-region analog trigger condition, the trigger signal is generated when the input analog signal level falls in the range between the High_Threshold and the Low_Threshold voltages. NOTE The High_Threshold setting should be always higher than the Low_Threshold voltage setting.
Figure 4-35: High-Hysteresis Analog Trigger Condition Low-Hysteresis Analog Trigger Condition Figure 4-36 shows the low-hysteresis analog trigger condition, the trigger signal is generated when the input analog signal level is less than the Low_Threshold voltage, and the High_Threshold voltage determines the hysteresis duration. Note the High_Threshold setting should be always higher then the Low_Threshold voltage setting.
External Digital Trigger An external digital trigger occurs when a rising edge or a falling edge is detected on the digital signal connected to the EXTDTRIG or the EXTWFTRG of the 68-pin connector for external digital trigger. The EXTDTRIG is dedicated for A/D process, and the EXTWFTRG is used for D/A process. You can program the trigger polarity using the software drivers. Note that the signal level of the external digital trigger signals should be TTLcompatible and the minimum pulse is 20 ns.
4.6 User-controllable Timing Signals In order to meet the requirements for user-specific timing and requirements for synchronizing multiple cards, the DAQ-/DAQe-/ PXI-2204/2205/2206/2208 card provides flexible user-controllable timing signals to connect to external circuitry or additional cards. The whole DAQ timing of the DAQ-/DAQe-/PXI-2204/2205/2206/ 2208 card is composed of a bunch of counters and trigger signals in the FPGA.
You can utilize the flexible timing signals through our software drivers, then simply and correctly connect the signals with the DAQ-/DAQe-/PXI-2204/2205/2206/2208 card. Here is the summary of the DAQ timing signals and the corresponding functionalities for DAQ-/DAQe-/PXI-2204/2205/2206/2208 card.
width of the TIMEBASE to guarantee correct functionalities. 4. ADCONV, the conversion signal to initiate a single conversion, which could be derived from internal counter, AFI[0] or SSI_ADCONV. Note that this signal is edgesensitive. When using AFI[0] as the external ADCONV source, each rising edge of AFI[0] would bring an effective conversion signal. Also note that the AFI[0] signal should be TTL-compatible and the minimum pulse width is 20 ns. 5.
Auxiliary Function Inputs (AFI) You can use the AFI in applications that take advantage of external circuitry to directly control the DAQ-/DAQe-/PXI-2204/2205/ 2206/2208 card. The AFI includes two categories of timing signals: one group is the dedicated input, and the other is the multi-function input. Table 4-9 illustrates this categorization.
intervals for both A/D and D/A operations. Note that once you choose the TIMEBASE source, both A/D and D/A operations will be affected because A/D and D/A operations share the same TIMEBASE. AFI[0] Alternatively, you can also directly apply an external A/D conversion signal to replace the internal ADCONV signal. This is another way to achieve customized sampling frequencies. The external ADCONV signal can only be inputted from the AFI[0]. As section 4.
System Synchronization Interface SSI (System Synchronization Interface) provides the DAQ timing synchronization between multiple cards. In DAQ-/DAQe-/PXI2204/2205/2206/2208 card, we designed a bi-directional SSI I/O to provide flexible connection between cards and allow one SSI master to output the signal and up to three slaves to receive the SSI signal. Note that the SSI signals are designed for card synchronization only and not for external devices.
In PXI form factor, we utilize the PXI trigger bus built on the PXI backplane to provide the necessary timing signal connections. All the SSI signals are routed to the P2 connector. No additional cable is needed. For detailed information of the PXI specifications, refer to the PXI Specification Revision 2.0 from PXI System Alliance (www.pxisa.org). The six internal timing signals could be routed to the SSI or the PXI trigger bus through software drivers. Refer to section 4.
The SSI/PXI Mechanism We adopt master-slave configuration for SSI/PXI. In a system, for each timing signal, there shall be only one master, and other cards are SSI slaves or with SSI function disabled. For each timing signal, the SSI master does not have to be in a single card. For example: We want to synchronize the A/D operation through the ADCONV signal for four DAQ-/DAQe-/PXI-2204/2205/2206/ 2208 cards. Card 1 is the master, and Card 2, 3, 4 are slaves.
5 Calibration This chapter introduces the calibration process to minimize AD measurement errors and DA output errors. 5.1 Loading Calibration Constants The DAQ-/DAQe-/PXI-2204/2205/2206/2208 card is factory-calibrated before shipment. The associated calibration constants of the TrimDACs firmware to the onboard EEPROM. TrimDACs are devices containing multiple DACs within a single package. TrimDACs do not have memory capability.
5.2 Auto-calibration Through the DAQ-/DAQe-/PXI-2204/2205/2206/2208 card autocalibration feature, the calibration software measures and corrects almost all calibration errors without any external signal connections, reference voltage, or measurement devices. The DAQ-/DAQe-/PXI-2204/2205/2206/2208 card comes with an onboard calibration reference to ensure the accuracy of auto-calibration. The reference voltage is measured in the production line through a digital potentiometer and compensated in the software.
Warranty Policy Thank you for choosing ADLINK. To understand your rights and enjoy all the after-sales services we offer, please read the following carefully. 1. Before using ADLINK’s products please read the user manual and follow the instructions exactly. When sending in damaged products for repair, please attach an RMA application form which can be downloaded from: http:// rma.adlinktech.com/policy/. 2.
3. Our repair service is not covered by ADLINK's guarantee in the following situations: X Damage caused by not following instructions in the User's Manual. X Damage caused by carelessness on the user's part during product transportation. X Damage caused by fire, earthquakes, floods, lightening, pollution, other acts of God, and/or incorrect usage of voltage transformers. X Damage caused by unsuitable storage environments (i.e. high temperatures, high humidity, or volatile chemicals).
