User manual

51 Chapter 3
Inter(R) speedstep(tm) tech
Intel SpeedStep Technology centralizes the control mechanism in the
processor, eliminating the need for coordination with the chipset during
the frequency/voltage configuration. This option is used to enable/disable
the GV3 bit.
3.3.2 IDE Configuration
Figure 3.6: IDE Configuration
ATA/IDE Configuration
This can be configured as Disabled, Compatible or Enhanced.
Configure SATA as
This can be configured as IDE, RAID or AHCI. RAID will be activated
by the ICH8M-E only.
Primary IDE Master
While entering setup, the BIOS automatically detects the presence of IDE
devices. This displays the status of IDE device auto-detection.