PCI-1710/1710HG Multifunction DAS Card for PCI Bus User's manual
Copyright This documentation and the software included with this product are copyrighted 1998 by Advantech Co., Ltd. All rights are reserved. Advantech Co., Ltd. reserves the right to make improvements in the products described in this manual at any time without notice. No part of this manual may be reproduced, copied, translated or transmitted in any form or by any means without the prior written permission of Advantech Co., Ltd. Information provided in this manual is intended to be accurate and reliable.
Contents Chapter 1: General Information ............................. 1 1.1 1.2 1.3 1.4 Introduction ............................................................... 2 Features .................................................................... 3 Specifications............................................................. 4 Block Diagram........................................................... 8 Chapter 2: Installation .............................................. 9 2.1 2.2 2.3 Initial Inspection .....
.7 4.8 4.9 4.10 4.11 4.12 4.13 4.14 Control Register....................................................... 39 Status Register ......................................................... 40 Clear Interrupt and FIFO ......................................... 41 D/A Channel 0 Output ............................................. 42 D/A Channel 1 Output ............................................. 42 D/A Reference Control ............................................ 43 Digital I/O Registers ....................
CHAPTER 1 General Information Chapter 1 General Information 1
1.1 Introduction The PCI-1710/1710HG is a multifunction DAS card for the PCI bus. Advanced circuit design brings you higher quality and more functions, including the five most desired measurement and control functions: 12-bit A/D conversion, D/A conversion, digital input, digital output, and counter/timer. PCI-bus Plug and Play The PCI-1710/1710HG uses a PCI controller to interface the card with the PCI bus. The controller fully implements the PCI bus specification Rev 2.1.
On-board Programmable Counter The PCI-1710/1710HG provides a programmable counter for generating a pacer trigger for the A/D conversion. The counter chip is an 82C54 or equivalent, which includes three 16-bit counters on a 10 MHz clock. One counter is used as an event counter for counting events coming from the input channels. The other two are cascaded together to make a 32-bit timer for a pacer trigger. 1.
1.3 Specifications Analog Input: • Channels: 16 single-ended or 8 differential (software programmable) • Resolution: 12-bit • On-board FIFO: 4K samples • Conversion time: 8 µs • Input range: (V, software programmable) PCI-1710 PCI-1710HG Bipolar ±10, ±5, ±2.5, ±1.25, ±0.625 ±10, ±5, ±1, ±0.5, ±0.1, ±0.05, ±0.01, ±0.005 Unipolar 0 ~ 10, 0 ~ 5, 0 ~ 2.5, 0 ~ 1.25 0 ~ 10, 0 ~ 1, 0 ~ 0.1, 0 ~ 0.
• Maximum data throughput: PCI-1710: 100 kHz PCI-1710HG: (variable, depending on PGIA settling time) PCI-1710HG Gain Speed 0.5, 1 100 kHz 5, 10 35 kHz 50, 100 7 kHz 500, 1000 770 Hz • Accuracy: (depending on gain) PCI-1710 PCI-1710HG Gain Accuracy Gain Accuracy Remark 0.5, 1 0.01% of FSR ±1 LSB 0.5, 1 0.01% of FSR ±1 LSB S.E./D* 2 0.02% of FSR ±1 LSB 5, 10 0.02% of FSR ±1 LSB S.E./D 4 0.02% of FSR ±1 LSB 50, 100 0.04% of FSR ±1 LSB D 8 0.04% of FSR ±1 LSB 500, 1000 0.
Analog Output: • Channels: 2 • Resolution: 12-bit • Relative accuracy: ±1/2 LSB • Gain error: ±1 LSB • Maximum update rate: 100 K samples/s • Slew rate: 10 V/µs • Output range: (software programmable) With internal reference: 0 ~ +5 V, 0 ~ +10 V With external reference: 0 ~ +x V @ -x V (-10 ≤ x ≤ 10) Digital Input: • Channels: 16 • Input voltage: Low: 0.4 V max. High: 2.4 V min. • Input load: Low: -0.2 mA @ 0.4 V High: 20 µA @ 2.7 V Digital Output: • Channels: 16 • Output voltage: Low: 0.4 V max. @ 8.
Programmable Timer/Counter • Counter chip: 82C54 or equivalent • Counters: 3 channels, 16 bits, 2 channels are permanently configured as programmable pacers; 1 channel is free for user application • Input, gate: TTL/CMOS compatible • Time base: Channel 1:10 MHz Channel 2:Takes input from output of channel 1 Channel 0:Internal 1 MHz or external clock (10 MHz max.) selected by software. General: • I/O Connector: 68-pin SCSI-II female connector • Power consumption: +5 V @ 850 mA (Typical), +5 V @ 1.0 A (Max.
1.
CHAPTER 2 Installation Chapter 2 Installation 9
2.1 Initial Inspection Before installing the PCI-1710/1710HG, check the card for visible damage. We have carefully inspected the card both mechanically and electrically before shipment. It should be free of marks and in perfect order upon receipt. As you unpack the PCI-1710/1710HG, check it for signs of shipping damage (damaged box, scratches, dents, etc.). If it is damaged or fails to meet specifications, notify our service department or your local sales representative immediately.
2.3 Installation Instructions The PCI-1710/1710HG can be installed in any PCI slot in the computer. However, refer to the computer user's manual to avoid any mistakes and danger before you follow the installation procedure below: 1. Turn off your computer and any accessories connected to the computer. Warning! TURN OFF your computer power supply whenever you install or remove any card, or connect and disconnect cables. 2. Disconnect the power cord and any other cables from the back of the computer. 3.
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CHAPTER 3 Signal Connections Chapter 3 Signal Connections 13
3.1 Overview Correct signal connections are one of the most important factors in ensuring that your application system is sending and receiving data correctly. A good signal connection can avoid much unnecessary and costly damage to your valuable PC and other hardware devices. This chapter will provide some useful information about how to connect input and output signals to the PCI-1710/1710HG card via the I/O connector. 3.
AI0 AI2 AI4 AI6 AI8 AI10 AI12 AI14 AIGND DA0_REF DA0_OUT AOGND DI0 DI2 DI4 DI6 DI8 DI10 DI12 DI14 DGND DO0 DO2 DO4 DO6 DO8 DO10 DO12 DO14 DGND CNT0_CLK CNT0_OUT CNT0_GATE +12V 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 AI1 AI3 AI5 AI7 AI9 AI11 AI13 AI15 AIGND DA1_REF DA1_OUT AOGND DI1 DI3 DI5 DI7 DI9 DI11 DI13 DI15 DGND DO1 DO3 DO5 DO7 DO9 DO11 DO13 DO15
I/O Connector Signal Descriptions Signal Name Reference Direction Description AI<0…15> AIGND Input Analog Input Channels 0 through 15. Each channel pair, AI (i = 0, 2, 4...14), can be configured as either two single-ended inputs or one differential input. AIGND - - Analog Input Ground. These pins are the reference points for single-ended measurements and the bias current return point for differential measurement.
I/O Connector Signal Descriptions (part II) Signal Name Reference Direction DI<0..15> DGND Input DO<0..15> DGND Output DGND - - CNT0_ CLK DGND Input CNT0 _OUT DGND Output CNT0 _GATE DGND Input Description Digital Input signals Digital Output signals Digital Ground. This pin supplies the reference for the digital signals at the I/O connector as well as the +5V DC supply. The three ground references (AIGND, AOGND, and DGND) are connected together on the PCI-1710/1710HG card.
I/O Connector Signal Descriptions (part III) Signal Name PACER _OUT TRG _GATE 18 Reference DGND DGND Direction Description Output Pacer Clock Output - This pin pulses once for each pacer clock when turned on. If A/D conversion is in the pacer trigger mode, users can use this signal as a synchronous signal for other applications. A low-to-high edge triggers A/D conversion to start. Input A/D External Trigger Gate - This pin is external trigger signal input gate control.
3.3 Analog Input Connections The PCI-1710/1710HG card supports either 16 single-ended or 8 differential analog inputs. Input channel configuration is selected by software. Selection by software is more convenient than selection by a slide switch on the card. In the past, if you set one single-ended (or differential) input channel by switch, the other channels also would be single-ended (or differential).
Internal External Figure 3-2: Single-ended input channel connection Differential Channel Connections The differential input configuration has two signal wires for each channel, and the differential input responds only to voltage differences between High and Low inputs. On the PCI-1710/1710HG card, when all channels are configured to differential input, up to 8 analog channels are available. If one side of the signal source is connected to a local ground, the signal source is ground-referenced.
card. With this connection, the PGIA rejects a common-mode voltage Vcm between the signal source and the PCI-1710/1710HG ground, shown as Vcm in Figure 3-3. Internal External Figure 3-3: Differential input channel connection - ground reference signal source If a floating signal source is connected to the differential input channel, the signal source may exceed the common-mode signal range of the PGIA, and the PGIA will be saturated with erroneous voltagereadings.
Internal External ra rb Figure 3-4: Differential input channel connection - floating signal source However, this connection has the disadvantage of loading the source down with the series combination (sum) of the two resistors. For ra and rb, for example, if the input impedance rs is 1 kΩ, and each of the two resistors is 100 kΩ, then the resistors load down the signal source with 200 kΩ (100 kΩ + 100 kΩ), resulting in a –0.5% gain error.
3.4 Analog Output Connections The PCI-1710/1710HG card provides two D/A output channels, DA0_OUT and DA1_OUT. Users may use the PCI-1710/1710HG internally provided precision –5V (-10V) reference to generate 0 to +5 V (+10 V) D/A output range. Users also may create D/A output range through external references, DA0_REF and DA1_REF. The maximum reference input range is +/-10 V. Connecting with an external reference of -7 V will generate 0 to +7 V DA output.
3.5 Trigger Source Connections Internal Pacer Trigger Connection The PCI-1710/1710HG card includes one 82C54 compatible programmable timer/counter chip which provides three 16-bit counters connected to a 1 MHz clock, designated as Counter 0, Counter 1 and Counter 2. Counter 0 is an event counter for counting events coming from the input channels. Counter 1 and Counter 2 are cascaded to create a 32bit timer for pacer triggering.
3.6 Field Wiring Considerations When you use the PCI-1710/1710HG card to acquire outside data, environmental noise can seriously affect the accuracy of your measurements if you don’t provide any protection. The following suggestions will be helpful when running signal wires between signal sources and the PCI-1710/1710HG card. • Please make sure that you have carefully routed signal cables to the card. You must separate the cabling from noise sources.
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CHAPTER 4 Register Structure and Format Chapter 4 Register Structure and Format 27
4.1 Overview The PCI-1710/1710HG is delivered with an easy-to-use 32-bit DLL driver for user programming under the Windows 95/NT operating system. We advise users to program the PCI-1710/1710HG using the 32-bit DLL driver provided by Advantech to avoid the complexity of low-level programming by register. The most important consideration in programming the PCI-1710/ 1710HG card at a register level is to understand the function of the card’s registers.
Table 4-1: PCI-1710/1710HG register format (Part 1) Base Address + decimal Read 7 6 5 4 3 2 1 0 Channel Number and A/D Data 1 CH3 CH2 CH1 CH0 AD11 AD10 AD9 AD8 0 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 IRQ F/F F/H F/E GATE EXT PACER SW N/A 3 2 N/A 5 4 Status Register 7 6 CNT0 ONE/FH IRQEN N/A 9 8 N/A 11 10 N/A 13 12 Chapter 4 Register Structure and Format 29
Table 4-1: PCI-1710/1710HG register format (Part 2) Base Address + decimal Read 7 6 5 4 3 2 1 0 N/A 15 14 Digital Input 17 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8 16 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 D2 D1 D0 D2 D1 D0 D2 D1 D0 Counter 0 25 24 D7 D6 D5 D4 D3 Counter 1 27 26 D7 D6 D5 D4 D3 Counter 2 29 28 D7 D6 D5 D4 D3 N/A 31 30 30 PCI-1710/1710HG User's Manual
Table 4-1: PCI-1710/1710HG register format (Part 3) Base Address + decimal Write 7 6 5 4 3 2 1 0 G1 G0 Software A/D Trigger 1 0 A/D Channel Range Setting 3 2 S/D B/U G2 MUX Control 5 Stop channel 4 Start channel Control Register 7 6 CNT0 ONE/FH IRQEN GATE EXT PACER SW DA11 DA10 DA9 DA8 DA3 DA1 DA0 DA11 DA10 DA9 DA8 DA3 DA1 DA0 Clear Interrupt and FIFO 9 clear FIFO 8 clear interrupt D/A Output Channel 0 11 10 DA7 DA6 DA5 DA4 DA2 D/A Output Channel 1 13 12 DA7
Table 4-1: PCI-1710/1710HG register format (Part 4) Base Address + decimal Write 7 6 5 4 3 2 1 0 DA1_5/10 DA0_I/E DA0_5/10 D/A Reference Control 15 14 DA1_I/E Digital Output 17 DO15 DO14 DO13 DO12 DO11 DO10 DO9 DO8 16 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 D2 D1 D0 D2 D1 D0 D2 D1 D0 D2 D1 D0 Counter 0 25 24 D7 D6 D5 D4 D3 Counter 1 27 26 D7 D6 D5 D4 D3 Counter 2 29 28 D7 D6 D5 D4 D3 Counter Control 31 30 32 D7 D6 PCI-1710/1710HG User's Manual D5 D
4.3 Channel Number and A/D Data BASE+0 and BASE+1 These two bytes, BASE+0 and BASE+1, hold the result of A/D conversion data. The 12 bits of data from the A/D conversion are stored in BASE+1 bit 3 to bit 0 and BASE+0 bit 7 to bit 0. BASE+1 bit 7 to bit 4 hold the source A/D channel number.
4.5 A/D Channel Range Setting BASE+2 Each A/D channel has its own input range, controlled by a range code stored in the on-board RAM. If you want to change the range code for a given channel, select the channel as the start channel and the stop channel in the registers of BASE+4 and BASE+5 (described in the next section), and then write the range code to BASE+2 bit 0 to bit 2 and bit 4.
The following table lists the gain codes for the PCI-1710: Table 4-4: Gain codes for the PCI-1710 PCI-1710 Gain Code Gain Input Range(V) B/U G2 G1 G0 1 -5 to +5 0 0 0 0 2 -2.5 to +2.5 0 0 0 1 4 -1.25 to +1.25 0 0 1 0 8 -0.625 to +0.625 0 0 1 1 0.5 -10 to 10 0 1 0 0 N/A 0 1 0 1 N/A 0 1 1 0 N/A 0 1 1 1 1 0 to 10 1 0 0 0 2 0 to 5 1 0 0 1 4 0 to 2.5 1 0 1 0 8 0 to 1.
The following lists the gain codes for the PCI-1710HG: Table 4-5: Gain codes for the PCI-1710HG PCI-1710HG Gain Code Gain 36 Input Range(V) B/U G2 G1 G0 1 -5 to +5 0 0 0 0 10 -0.5 to +0.5 0 0 0 1 100 -0.05 to +0.05 0 0 1 0 1000 -0.005 to +0.005 0 0 1 1 0.5 -10 to +10 0 1 0 0 5 -1 to +1 0 1 0 1 50 -0.1 to +0.1 0 1 1 0 500 -0.01 to +0.01 0 1 1 1 1 0 to 10 1 0 0 0 10 0 to 1 1 0 0 1 100 0 to 0.1 1 0 1 0 1000 0 to 0.
4.6 MUX ControlBASE+4 and BASE+5 Table 4.6: The register for multiplexer control Write Bit # MUX Control 3 2 1 0 BASE+5 7 6 5 4 CH3 CH2 CH1 CH0 BASE+4 CL3 CL2 CL1 CL0 CL3 ~ CL0 Start Scan Channel Number CH3 ~ CH0 Stop Scan Channel Number BASE+4 bit 3 to bit 0, CL3 ~ CL0, act as a pointer when you program the A/D channel setting (see previous section).
the stop channel and then repeat. The following examples show the scan sequences of the MUXs (all channels are set as single-ended).
differential, and AI14 is differential, then the scan sequence is AI11, AI12, AI14, AI11, AI12, AI14, AI11… Warning! Only even channels can be set as differential. An odd channel will become unavailable if its preceding channel is set as differential. 4.7 Control Register BASE+6 The write-only register BASE+6 allows users to set an A/D trigger source and an interrupt source.
GATE External trigger gate function enable bit Set 1 to enable external trigger gate function, and set 0 to disable. IRQEN Interrupt enable bit Set 1 to enable interrupt, and set 0 to disable. ONE/FH Interrupt source bit Set 0 to interrupt when an A/D conversion occurs, and set 1 to interrupt when the FIFO is half full.
F/H FIFO Half-full flag This bit indicates whether the FIFO is half-full. 1 means that the FIFO is half-full. F/F FIFO Full flag This bit indicates whether the FIFO is full. 1 means that the FIFO is full. IRQ Interrupt flag This bit indicates the interrupt status. 1 means that an interrupt has occurred. 4.9 Clear Interrupt and FIFO BASE+8 and BASE+9 Writing data to either of these two bytes clears the interrupt or the FIFO.
4.10 D/A Output Channel 0 BASE+10 and BASE+11 The write-only registers of BASE+10 and BASE+11 accept data for D/A Channel 0 output. Table 4-10: Registers for D/A channel 0 data Write Bit # D/A Output Channel 7 6 5 4 DA7 DA6 DA5 DA4 BASE+11 BASE+10 3 2 1 0 DA11 DA10 DA9 DA8 DA3 DA2 DA1 DA0 DA11 ~ DA0 Digital to Analog data DA0 is the LSB and DA11 is the MSB of the D/A data. 4.
4.12 D/A Reference Control BASE+14 The write-only register of BASE+14 allows users to set the D/A reference source. Table 4-12: Registers for D/A reference control Write Bit # BASE+14 D/A Reference Control 7 6 5 4 3 2 1 0 DA1_I/E DA1_5/10 DA0_I/E DA0_5/10 DA0_5/10 The internal reference voltage for the D/A output channel 0 This bit controls the internal reference voltage for the D/A output channel 0. 0 means that the internal reference voltage is 5 V, and 1 means it is 10 V.
4.13 Digital I/O Registers BASE+16 and BASE+17 The PCI-1710/1710HG card offers 16 digital input channels and 16 digital output channels. These I/O channels use the input and output ports at addresses BASE+16 and BASE+17.
CHAPTER 5 Calibration Chapter 5 Calibration 45
5.1 Introduction Regular calibration checks are important to maintain accuracy in data acquisition and control applications. We provide two calibration programs, ADCAL.EXE and DACAL.EXE, on the PCI-1710/1710HG software CD-ROM. ADCAL.EXE assists you in A/D calibration, and DACAL.EXE in D/A calibration. The ADCAL.EXE and DACAL.EXE make calibrations easy.
The following list shows the function of each VR: VR VR1 Function A/D unipolar offset VR2 A/D bipolar offset VR3 A/D full scale (gain) VR4 D/A channel 0 full scale VR5 D/A channel 1 full scale 5.3 A/D Calibration Regular and accurate calibration procedures ensure the maximum possible accuracy. The ADCAL.EXE calibration program leads you through the whole A/D offset and gain adjustment procedure. The basic steps are outlined below: 1.
A/D code Mapping Voltage Hex. Dec. Bipolar ± 5V Unipolar 0 to 10V 000h 0 -4.9971V 0V 7FFh 2047 -0.0024V 4.9947V 800h 2048 0V 4.9971V FFFh 4095 +4.9947V 9.9918V 5.4 D/A Calibration In a way similar to the ADCAL.EXE program, the DACAL.EXE program leads you through the whole D/A calibration procedure. You can either use the on-board -5 V (-10 V) internal reference voltage or use an external reference.
5.5 Self A/D Calibration Under many conditions, it is difficult to find a good enough DC voltage source for A/D calibration. There is a simple method to solve this problem. First, you should calibrate D/A channel 0, DA0_OUT, with internal reference -5 V, and D/A channel 1, DA1_OUT, with reference -10 V. Then, run the ADCAL.EXE program to finish the self-A/D calibration procedure. 1. Set AI0 as differential, bipolar, range ±5 V and AI2 as differential, unipolar, range 0 to 10 V. 2.
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APPENDIX A 82C54 Counter Chip Functions Appendix A 8524 Counter Chip Functions 51
A.1 The Intel 82C54 The PCI-1710/1710HG uses one Intel 82C54 compatible programmable interval timer/counter chip. The popular 82C54 offers three independent 16-bit counters, counter 0, counter 1 and counter 2. Each counter has a clock input, control gate and an output. You can program each counter for maximum count values from 2 to 65535. The 82C54 has a maximum input clock frequency of 1 MHz. The PCI-1710/1710HG provides 1 MHz input frequencies to the counter chip from an on-board crystal oscillator.
A.2 Counter Read/Write and Control Registers The 82C54 programmable interval timer uses four registers at addresses BASE + 24(Dec), BASE + 26(Dec), BASE + 28(Dec) and BASE + 30(Dec) for read, write and control of counter functions.
RW1 & RW0 Select read/write operation Operation Counter latch RW1 0 RW0 0 Read/write LSB 0 1 Read/write MSB 1 0 Read/write LSB first, then MSB 1 1 M2, M1 & M0 Select operating mode M2 0 M1 0 M0 0 Mode 0 Description Stop on terminal count 0 0 1 1 Programmable one shot X 1 0 2 Rate generator X 1 1 3 Square wave rate generator 1 0 0 4 Software triggered strobe 1 0 1 5 Hardware triggered strobe BCD Select binary or BCD counting.
becomes: BASE + 30(Dec) 82C54 control, read-back mode Bit D7 D6 D5 D4 D3 D2 D1 D0 Value C0 X 1 1 CNT STA C2 C1 CNT = 0 Latch count of selected counter(s). STA = 0 Latch status of selected counter(s). C2, C1 & C0 Select counter for a read-back operation. C2 = 1 select Counter 2 C1 = 1 select Counter 1 C0 = 1 select Counter 0 If you set both SC1 and SC0 to 1 and STA to 0, the register selected by C2 to C0 contains a byte which shows the status of the counter.
A.3 Counter Operating Modes MODE 0 Stop on Terminal Count The output will initially be low after you set this mode of operation. After you load the count into the selected count register, the output will remain low and the counter will count. When the counter reaches the terminal count, its output will go high and remain high until you reload it with the mode or a new count value. The counter continues to decrement after it reaches the terminal count.
The gate input, when low, will force the output high. When the gate input goes high, the counter will start from the initial count. You can thus use the gate input to synchronize the counter. With this mode the output will remain high until you load the count register. You can also synchronize the output by software.
A.4 Counter Operations Read/Write Operation Before you write the initial count to each counter, you must first specify the read/write operation type, operating mode and counter type in the control byte and write the control byte to the control register [BASE + 30(Dec)]. Since the control byte register and all three counter read/write registers have separate addresses and each control byte specifies the counter it applies to (by SC1 and SC0), no instructions on the operating sequence are required.
Counter Latch Operation Users often want to read the value of a counter without disturbing the count in progress. You do this by latching the count value for the specific counter then reading the value. The 82C54 supports the counter latch operation in two ways. The first way is to set bits RW1 and RW0 to 0. This latches the count of the selected counter in a 16-bit hold register. The second way is to perform a latch operation under the read-back command. Set bits SC1 and SC0 to 1 and CNT = 0.
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