User manual

SOM-4430 User Manual 22
B.1 GPIO Register
Table B.1: BASE_ADDR defined on SB PCI CFG 61-60h
Bit Name P/W PWR Description
7-0 PORT0DT RW +V 5 PORT0 GPIO[7-0] data
Table B.2: BASE_ADDR defined on SB PCI CFG 63-62h
Bit Name P/W PWR Description
7-0 PORT1DT RW +V 5 PORT1 GPIO[15-8] data
Table B.3: BASE_ADDR defined on SB PCI CFG 65-64h
Bit Name P/W PWR Description
7-0 PORT2DT RW +V 5 PORT2 GPIO[23-16] data
Table B.4: BASE_ADDR defined on SB PCI CFG 67-66h
Bit Name P/W PWR Description
7-0 PORT3DT RW +V 5 PORT3 GPIO[31-24] data
Table B.5: BASE_ADDR defined on SB PCI CFG 69-68h
Bit Name P/W PWR Description
7-0 PORT4 DT RW +V 5 PORT4 GPIO[39-32] data
Table B.6: BASE_ADDR defined on SB PCI CFG 6B-6Ah
Bit Name P/W PWR Description
7-0 PORT0 DT RW +V 5 PORT0 GPIO[7-0] Setting
0: Direction is INPUT
1: Direction is OUTPUT
7-0 PORT1 DT RW +V 5 PORT1 GPIO[15-8] Setting
0: Direction is INPUT
1: Direction is OUTPUT
7-0 PORT2 DT RW +V 5 PORT0 GPIO[23-16] Setting
0: Direction is INPUT
1: Direction is OUTPUT
7-0 PORT3 DT RW +V 5 PORT0 GPIO[31-24] Setting
0: Direction is INPUT
1: Direction is OUTPUT
7-0 PORT4 DT RW +V 5 PORT0 GPIO[39-32] Setting
0: Direction is INPUT
1: Direction is OUTPUT