User Manual MIC-3392 6U CompactPCI Intel Core 2 Duo Processor Based Board with Dual PCIe GbE/DDR2/SATA/PMC
Copyright The documentation and the software included with this product are copyrighted 2006 by Advantech Co., Ltd. All rights are reserved. Advantech Co., Ltd. reserves the right to make improvements in the products described in this manual at any time without notice. No part of this manual may be reproduced, copied, translated or transmitted in any form or by any means without the prior written permission of Advantech Co., Ltd. Information provided in this manual is intended to be accurate and reliable.
Declaration of Conformity CE This product has passed the CE test for environmental specifications when shielded cables are used for external wiring. We recommend the use of shielded cables. This kind of cable is available from Advantech. Please contact your local supplier for ordering information. FCC Class A Note: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of the FCC Rules.
Warnings, Cautions and Notes Warning! Warnings indicate conditions, which if not observed, can cause personal injury! Caution! Cautions are included to help you avoid damaging hardware or losing data. e.g. There is a danger of a new battery exploding if it is incorrectly installed. Do not attempt to recharge, force open, or heat the battery. Replace the battery only with the same or equivalent type recommended by the manufacturer. Discard used batteries according to the manufacturer's instructions.
Safety Instructions 1. 2. 3. Read these safety instructions carefully. Keep this User Manual for later reference. Disconnect this equipment from any AC outlet before cleaning. Use a damp cloth. Do not use liquid or spray detergents for cleaning. 4. For plug-in equipment, the power outlet socket must be located near the equipment and must be easily accessible. 5. Keep this equipment away from humidity. 6. Put this equipment on a reliable surface during installation.
Wichtige Sicherheishinweise 1. 2. 3. Bitte lesen sie Sich diese Hinweise sorgfältig durch. Heben Sie diese Anleitung für den späteren Gebrauch auf. Vor jedem Reinigen ist das Gerät vom Stromnetz zu trennen. Verwenden Sie Keine Flüssig-oder Aerosolreiniger. Am besten dient ein angefeuchtetes Tuch zur Reinigung. 4. Die NetzanschluBsteckdose soll nahe dem Gerät angebracht und leicht zugänglich sein. 5. Das Gerät ist vor Feuchtigkeit zu schützen. 6.
Safety Precaution - Static Electricity Follow these simple precautions to protect yourself from harm and the products from damage. ! To avoid electrical shock, always disconnect the power from your PC chassis before you work on it. Don't touch any components on the CPU card or other cards while the PC is on. ! Disconnect power before making any configuration changes. The sudden rush of power as you connect a jumper or install a card may damage sensitive electronic components.
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Contents Chapter 1 Hardware Configuration......................1 1.1 Introduction ............................................................................................... 2 Table 1.1: MIC-3392 Variants...................................................... 2 Specifications ............................................................................................ 2 1.2.1 CompactPCI Bus Interface ........................................................... 2 1.2.2 CPU ..............................
1.8 1.9 1.5.4 CompactFlash Socket (CN10) .................................................... 13 1.5.5 SATA daughter board connector (CN4) (Single PMC only)........ 13 1.5.6 Ethernet Configuration (RJ1/RJ2 or Rear I/O RJ1) .................... 14 1.5.7 PMC Connector (J23 for PMC1, Jxx for PMC2) ......................... 14 1.5.8 SW1 (System reset and BMC reset button)................................ 14 Safety Precautions..................................................................................
2.9.1 2.9.2 2.9.3 Chapter Save Changes and Exit .............................................................. 36 Discard Changes and Exit .......................................................... 36 Load Defaults.............................................................................. 36 3 IPMI .....................................................37 3.1 3.2 3.3 3.4 Introduction ............................................................................................. 38 Definitions ........
Appendix B Programming the Watchdog Timer . 55 B.1 Watchdog Timer Programming Procedure ............................................. 56 Appendix C CPLD .................................................. 57 C.1 C.2 Features.................................................................................................. 58 CPLD I/O Registers ................................................................................ 58 Table C.1: LPC I/O registers address ........................................
Chapter 1 1 Hardware Configuration This chapter describes how to configure MIC-3392 hardware.
1.1 Introduction The MIC-3392 is a high performance, power efficient CompactPCI single-board computer based on the Intel Core 2 Duo and Core Duo microprocessors. The MIC-3392 delivers breakthrough energy-efficient performance for CompactPCI platforms. The Intel Core 2 Duo provides enhanced energy-efficient performance to help equipment manufacturers optimally balance processing capabilities within power and space constraints.
1.2.3 Processor Table 1.2: Intel Processors Core speed Front-Side L2 cache Bus speed TDP Package Core Duo (T2500) 2.0 GHz 667 MHz 2 MB 31 W FCPGA LV Core Duo (L2400) 1.66 GHz 667 MHz 2 MB 15 W FCBGA Core 2 Duo (T7400) 2.16 GHz 667 MHz 4 MB 34 W FCPGA LV Core 2 Duo (L7400) 1.
1.2.6 Memory The MIC-3392 has up to 2 GB of onboard non-ECC DDR2 memory. In addition, an SODIMM socket supports up to 2 GB of the following types of memory. Table 1.
1.2.8 Storage interface The MIC-3392 supports two SATA interfaces and one IDE channel. The SATA1 interface can be routed to an onboard 2.5" SATA hard disk drive or to the rear I/O module via the J3 connector. The onboard SATA port is only available on the single PMC version of the MIC-3392. The SATA2 interface is connected to the rear I/O module via the J5 connector and is reserved for user customized designs. Currently, Advantech's compatible RIO modules provide the SATA1 interface.
1.2.14 Mechanical and Environmental Specifications ! Operating temperature: 0 ~ 55° C (32 ~ 122° F) Note! ! ! ! ! ! ! ! The operating temperature range of the MIC-3392 depends on the installed processor and the airflow through the chassis. Storage Temperature: -20 ~ 60° C (-4 ~ 140° F). Humidity (Non-operating): 5 ~ 95% @ 60° C (non-condensing) Power Consumption: (Intel Core 2 Duo and 2 GB memory) +5 V @ 7.16 A; +3.3 V @ 3.17 A; +12 V @ 0.40 A Board size: 233.
1.2.18 PMC (PCI Mezzanine Card) IEEE1386.1 Compliant Additional I/O or co-processing functionality is supported by add-on PMC modules. The MIC-3392 supports up to two PMC sites that are fully compliant with the IEEE1386.1 PCI Mezzanine Card specification. PMC1 supports a 64-bit / 66 MHz PCI bus interface whilst PMC2 supports a 32-bit / 33 MHz PCI bus interface. PMC1 supports 3.3 V VIO only, whereas PMC2 supports both 3.3 V and 5 V VIO. The two-layer front panel design complies with IEEE 1101.10.
1.2.23 HPET and IO/APIC The MIC-3392's built-in south bridge, the ICH7, provides features to support High Precision Event Timer (HPET) registers and I/O Advanced Programmable Interrupt Controller (APIC). The ICH7 timer registers are memory-mapped in a non-indexed scheme. The choice of address range will be selected by configuration bits in the HPET.
Table 1.4 and table 1.5 list the jumper and switch functions. Figure 1.2 illustrates the jumper and switch locations. Read this section carefully before changing the jumper and switch settings on your MIC-3392 board. Table 1.4: MIC-3392 jumper descriptions Function JP1 Clear CMOS JP2 VGA Output Setting JP14 PMC2 V(IO) setting JP4 PMC1 PCI bus frequency setting Hardware Configuration Number Table 1.
1.4.2 Clear CMOS (JP1) This jumper is used to erase CMOS data and reset the system BIOS information. Follow the procedures below to clear the CMOS. 1. Turn off the system. 2. Close jumper JP1 (1-2) for about 3 seconds. 3. Set jumper JP1 as Normal. 4. Turn on the system. The BIOS is reset to its default setting. Table 1.9: JP1 Clear CMOS Default Normal open Clear CMOS closed 1.4.3 Switch Settings Table 1.
Chapter 1 Table 1.13: SW5-3 & SW5-4: COM2 to console or BMC SW5-3 SW-5-4 On RIO COM2 to BMC On Off SIO COM2 to RIO Off Off When COM2 is not used as a console interface, it is used to communicate BMC information via the onboard SIO COM2 or RIO COM2. SW5-3 and SW5-4 determine whether COM2 is routed via SIO COM2 or RIO COM2. Three modes are available. SIO COM2 to BMC is the default. Table 1.
Figure 1.2 MIC-3392 jumper, switch and connector locations 1.5 Connector Definitions Onboard connectors link to external devices such as hard disk drives, keyboards or floppy drives. Table 1.11 lists the function of each connector and Figure 1.2 illustrates each connector location. Table 1.
1.5.2 Serial Ports (CN9 and Rear I/O) The MIC-3392 provides two serial ports. COM1 is available as an RS-232 interface via an RJ-45 connector on the front panel (CN9). An RJ-45 to DB-9 adaptor cable is provided in the MIC-3392 accessories to facilitate connectivity to external console or modem devices. Both the COM1 and COM2 ports are connected to the RIO-3310 series of rear I/O boards.
1.5.6 Ethernet Configuration (RJ1/RJ2 or Rear I/O RJ1) The MIC-3392 is equipped with two high performance, PCI-Express based, network interface controllers which provide fully compliant IEEE 802.3u 10/100/1000Base-TX Ethernet interfaces. Users can select front panel, rear I/O or PICMG 2.16 connectivity via the BIOS. Users can choose the LAN1 and LAN2 either via the front panel RJ-45 connectors (RJ1 and RJ2) or the RJ-45 connector (RJ1) on the rear I/O module.
Note! If your product comes with a processor in a soldered µFCBGA package, please add a different heat sink. You need to insert a heat pad between the processor and the heat sink. The heat pad is provided in the accessory bag. The heat pad should be positioned between the heat sink and the CPU. The heat pad is fragile, so please be careful during disassembly. If you are using a heat pad other than the one issued by Advantech, be aware that it may not absorb a sufficient amount of heat. Figure 1.
1.7.1 CPU & Heatsink Installation Steps The MIC-3392 contains electrostatically sensitive devices. Please discharge your clothing before touching the assembly. Do not touch components or connector pins. We recommend that you perform assembly at an anti-static workbench. 1. Check that the following components are close at hand: – 1 x CPU – Thermal paste – 1 x Heatsink – 4 x screws – 4 x springs 2. 3. Apply thermal paste to the top of the CPU die.
Fasten the heatsink to the base plate. Chapter 1 7. The battery model number is CR2032M1S8-LF, a 3 V, 210 mAH battery. Replacement batteries may be purchased from Advantech and replaced as described in the instructions below. Order the battery from Advantech using the following part number: 1750129010 -- BATTERY 3V/210 mAh with WIRE ASS'YCR2032M1S8-LF 1. Remove the battery from the board by unplugging the connector and pulling away the battery cover from the board. 2.
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Chapter 2 2 AMI BIOS Setup This chapter describes how to configure the AMI BIOS.
2.1 Introduction The AMI BIOS has been customized and integrated into many industrial and embedded motherboards for over a decade. This section describes the BIOS which has been specifically adapted to the MIC-3392. With the AMI BIOS Setup program, you can modify BIOS settings and control the special features of the MIC-3392. The Setup program uses a number of menus for making changes and turning the special features on or off. This chapter describes the basic navigation of the MIC-3392 setup screens.
Turn on the computer and check for the “patch” code. If there is a number assigned to the patch code, it means that BIOS supports your CPU. If there is no number assigned to the patch code, please contact an Advantech application engineer to obtain an up-to-date patch code file. This will ensure that your CPU's system status is valid. After ensuring that you have a number assigned to the patch code, press and you will immediately be allowed to enter Setup. Chapter 2 2.
2.3 Main Setup When you first enter the BIOS Setup Utility, you will enter the Main setup screen. You can always return to the Main setup screen by selecting the Main tab. Two main setup options are described in this section. The main BIOS setup screen is shown below. Figure 2.3 Main setup screen The main BIOS setup menu screen has two main frames. The left frame displays all the options that can be configured. “Grayed-out” options cannot be configured whilst options in blue can.
Select the Advanced tab from the MIC-3392 setup screen to enter the Advanced BIOS Setup screen. You can select any of the items in the left frame of the screen, such as CPU Configuration, to go to the sub menu for that item. You can display an Advanced BIOS Setup option by highlighting it using the keys. All Advanced BIOS Setup options are described in this section. The Advanced BIOS Setup screen is shown below. The sub menus are described on the following pages. Chapter 2 2.
2.4.1 CPU Configuration Figure 2.5 CPU Configuration 2.4.1.1 Max CPUID Value Limit It is recommended that you leave this value at the default setting of Disabled. Please note that this BIOS feature currently only allows the Intel Pentium 4 processor with Hyper-Threading Technology to work with operating systems that do not support extra CPUID information provided by the processor. 2.4.1.2 CPU TM function This item specifies the Thermal Monitor Feature.
Chapter 2 2.4.2 LAN & SMbus Configuration AMI BIOS Setup Figure 2.6 LAN & SMBus Configuration 2.4.2.1 Select LAN1/LAN2 mode The item allows you to choose where the LAN1 and LAN2 Gigabit Ethernet ports are connected. There are 3 options: Front (Default), PICMG 2.16 and Rear I/O board. 2.4.2.2 Select SMBus mode This setting indicates whether remote management is performed by Advantech's MIC-3924A Chassis Management Module (CMM) or by an IPMI-enabled CMM such as the Advantech MIC-3927.
2.4.3 IDE Configuration Figure 2.7 IDE Configuration 2.4.3.1 ATA/IDE Configuration Three options are available: Disabled, Compatible or Enhanced. “Disabled” means that all IDE resources are disabled. “Compatible” enables up to 2 IDE channels for OS's requiring legacy IDE operation (default setting) and “Enhanced” enables all SATA and PATA resources. 2.4.3.2 Legacy IDE Channels Four options are available: SATA Only, Reserved, “SATA Pri, PATA Sec” or PATA Only. 2.4.3.
Chapter 2 2.4.4 Floppy Configuration AMI BIOS Setup ! ! Figure 2.8 Floppy Configuration Floppy A: Select the type of floppy drive connected to the system. Floppy B: Select the type of floppy drive connected to the system.
2.4.5 Super I/O Configuration ! ! ! ! Figure 2.
Chapter 2 2.4.6 ACPI Setting AMI BIOS Setup Figure 2.10 ACPI Setting The options for “ACPI Aware O/S” are “Yes” or “No” in order to enable or disable ACPI support for the operating system. The default is “Yes”. 2.4.7 Hardware Health Configuration Figure 2.
2.4.8 Console Redirection Configuration Figure 2.12 Configure Remote Access types and parameters 2.4.8.1 Remote Access You can disable or enable the BIOS remote access feature here. The Optimal and Fail-Safe default setting is “Enabled”. 2.4.8.2 Serial Port Number Select the serial port you want to use for console redirection. You can set the value for this option to either ICH COM1 or ICH COM2. The Optimal and Fail-Safe default setting is ICH COM1. 2.4.8.
Select the PCI/PnP tab from the MIC-3392 setup screen to enter the Plug and Play BIOS Setup screen. You can display a Plug and Play BIOS Setup option by highlighting it using the keys. All Plug and Play BIOS Setup options are described in this section. The Plug and Play BIOS Setup screen is shown below. Chapter 2 2.5 PCI/PNP Setup AMI BIOS Setup Figure 2.13 PCI/PNP Setup 2.5.1 Clear NVRAM Set this value to force the BIOS to clear the Non-Volatile Random Access Memory (NVRAM).
2.6 Boot Setup Figure 2.14 Boot Setup 2.6.1 Boot Settings Configuration Figure 2.
! ! Quick Boot: Allows the BIOS to skip certain tests while booting. This will decrease the time needed to boot the system. Wait For 'F1' If Error: Wait for the F1 key to be pressed if an error occurs. Hit 'DEL' Message Display: Displays “Press DEL to run Setup” in POST. 2.7 Security Setup Chapter 2 ! AMI BIOS Setup Figure 2.16 Password Configuration Select Security Setup from the MIC-3392 Setup main BIOS setup menu.
2.8 Advanced Chipset Settings Figure 2.17 Advanced Chipset Setting 2.8.1 North Bridge Chipset Configuration Figure 2.
DRAM Frequency: Auto, 533MHz, 667MHz Boots Graphic Adapter Priority: Select which graphics controller to use as the primary boot device. 2.8.2 South Bridge Configuration Chapter 2 ! ! AMI BIOS Setup ! ! Figure 2.19 South Bridge Configuration USB 2.
2.9 Exit Option Figure 2.20 Exit Option 2.9.1 Save Changes and Exit When you have completed the system configuration changes, follow these steps: 1. Select Exit Saving Changes from the Exit menu and press . The following messages appear on the screen: Save Configuration Changes and Exit Now? [Ok] [Cancel] 2. Select Ok to save changes and exit. 2.9.2 Discard Changes and Exit Follow these steps to quit Setup without making any permanent changes to the system configuration. 1.
Chapter 3 3 IPMI This chapter describes IPMI configuration.
3.1 Introduction The MIC-3392 fully supports the IPMI 2.0 interface and the PICMG 2.9 R1.0 specification. The Renesas H8S/2167 has been implemented as the IPMI controller / Baseboard Management Controller (BMC) to run firmware and collect information. The MIC-3392 IPMI firmware is sourced from Avocent, a provider of proven and tested IPMI implementations in a wide range of mission-critical applications. The BMC's key features and functions are listed below. ! Compliant with IPMI specification, revision 2.
Table 3.1: Supported IPMI commands IPMI Device Global Commands Cmd Mandatory / Optional Get Device Id App 0x01 M Cold Reset App 0x02 O Get Self Test Results App 0x04 M Manufacturing Test On App 0x05 O Set ACPI Power State App 0x06 O Get ACPI Power State App 0x07 O Get Device GUID App 0x08 O 3.3.2 BMC Device and Messaging Interfaces The BMC messaging interfaces comply with the Intelligent Platform Management Interface Specification, Version 2.0.
Table 3.
Table 3.
3.3.7 SEL Device Commands Table 3.
Sensor data record (SDR) repository will be stored in BMC's flash memory and cannot be changed. Note! IPMI UNC = Upper Non-Critical. UC = Upper Critical UNR = Upper Non-Recoverable LNC = Lower Non-Critical LC = Lower Critical LNR = Lower Non-Recoverable Table 3.
Table 3.13: Threshold values of sensors Sensor Number 01h 02h 03h 04h 05h 00h Entity Instance 01h 01h 01h 01h 01h 01h Nominal Reading 3.3 V 2.5 V 5V 12 V 1.5 V 35° C UNR N/A N/A N/A N/A N/A 55° C UC 3.62 V 2.76 V 5.6 V 13.4 V 1.65 V N/A UNC N/A N/A N/A N/A N/A 45° C LNR N/A N/A N/A N/A N/A N/A LC 2.96 V 2.24 V 4.4 V 10.6 V 1.
The BMC can initiate a graceful shutdown of the MIC-3392 by issuing a short pulse (~500 ms) on the power button signal to the ACPI controller when commanded through its host, OOB, or IPMB channels as well as from a Graceful Shutdown Event from the CMM or a Handle OPEN event. An ACPI compliant OS will then perform a graceful shutdown and light the blue LED whereas a non-compliant OS will just shut down. The Network function (NetFn) field identifies the functional class of the message.
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Appendix A A Pin Assignments This appendix describes pin assignments.
A.1 J1 Connector Table A.1: J1 CompactPCI I/O Row A Row B Row C Row D Row E Row F 1 +5V -12V TRST# (NC) +12V +5V GND 2 TCK (NC) +5V TMS (NC) TDO TDI (NC) GND 3 INTA# INTB# INTC# +5V INTD# GND 4 IPMB_PWR HEALTHY# V(I/O) INTP INTS GND 5 NC NC PCI_RST# GND GNT0# GND 6 REQ0# PCI_PRESENT +3.3V CLK0 AD31 GND 7 AD30 AD29 AD28 GND AD27 GND 8 AD26 GND V(I/O) AD25 AD24 GND 9 C/BE3# IDSEL AD23 GND AD22 GND 10 AD21 GND +3.
Table A.
A.3 J3 Connector Table A.3: J3 CompactPCI I/O (LPT, FDD, Parallel IDE, 2.
Table A.
Table A.6: CN9 COM1 (RJ45) Connector 1 DCD# 6 DSR# 2 SIN 7 RTS# 3 SOUT 8 CTS# 4 DTR# 5 GND Table A.7: CN4 & CN5 USB port 1 & port 2 1 +5V (fused) 1 +5V (fused) 2 USBD0- 2 USBD1- 3 USBD0+ 3 USBD1+ 4 GND 4 GND 2 GND Table A.8: BT1 CMOS battery 1 BAT_VCC Table A.
1 GND 2 GND 3 GND 4 SATA_TX0P 5 GND 6 SATA_TX0N 7 GND 8 GND 9 GND 10 SATA_RX0N 11 GND 12 SATA_RX0P 13 GND 14 GND 15 RSV (+3.3V/+12V) 16 +5V 17 RSV (+3.3V/+12V) 18 +5V 19 RSV (+3.3V/+12V) 20 +5V Table A.11: RJ1 LAN1 Connector 1 LANMDI_0+ 5 LANMDI_2- 2 LANMDI_0- 6 LANMDI_1- 3 LANMDI_1+ 7 LANMDI_3+ 4 LANMDI_2+ 8 LANMDI_3- Table A.12: RJ1 LAN1 Indicator 53 MIC-3392 User Manual Appendix A Pin Assignments Table A.
A.5.1 M/D, PWR & IDE/Hot-swap LEDs 1 2 3 Name Description 1 M/D (Green) Indicates Master or Drone mode status 2 PWR (Green) Indicates the power status 3 IDE / Hot-swap (Yellow/Blue) Indicates IDE activity when yellow, or that the board is ready to be hot-swapped when blue.
Appendix B B Programming the Watchdog Timer This appendix describes how to program the watchdog timer.
B.1 Watchdog Timer Programming Procedure To program the watchdog timer, you must execute a program that writes a value to I/ O port address 443/444 (hex) for Enable/Disable. This output value represents time interval. The value range is from 01 (hex) to FF (hex), and the related time interval is 1 to 255 seconds. Data Time Interval 01 1 sec. 02 2 sec. 03 3 sec. 04 4 sec. … … 3F 63 sec.
Appendix C C CPLD This appendix describes CPLD configuration.
C.1 Features ! ! ! ! ! ! Drone Mode Hot-Swap: Hot insertion and removal control CompactPCI Backplane: CompactPCI slot Addressing LPC Bus: Provide LPC Bus access Watchdog Debug Message: Boot time POST message C.2 CPLD I/O Registers The Advantech MIC-3392 CPLD communicates with four main I/O spaces. The LPC (low pin count) Unit is used to interconnect the Intel ICH7M LPC signals. The Debug Port Unit is used to decode POST codes.
Table C.4: Watchdog [7:0] (LPC I/O address: 444H) Bits Name Default Valid State State 7~0 Watchdog xxh xxh Read Only Function Reading I/O port 444h will disable the watchdog. The return value is meaningless. Table C.5: Version [7:0] (LPC I/O address: 445H) Bits Name Default Valid State State Read Only Function 7~4 CPLD Ver- xxh sion (units) xxh Read I/O port 444h to get the CPLD version in BCD. E.g, for v1.
www.advantech.com Please verify specifications before quoting. This guide is intended for reference purposes only. All product specifications are subject to change without notice. No part of this publication may be reproduced in any form or by any means, electronic, photocopying, recording or otherwise, without prior written permission of the publisher. All brand and product names are trademarks or registered trademarks of their respective companies. © Advantech Co., Ltd.
