User Manual MIC-5332 AdvancedTCA® 10GbE Dual Socket CPU Blade with Intel® Xeon® E5-2600 series EP Processors
Revision History Revision Index 0.1 Brief Description of Changes Date of Issue Initial Draft 0.2 0.3 0.
Copyright The documentation and the software included with this product are copyrighted 2012 by Advantech Co., Ltd. All rights are reserved. Advantech Co., Ltd. reserves the right to make improvements in the products described in this manual at any time without notice. No part of this manual may be reproduced, copied, translated or transmitted in any form or by any means without the prior written permission of Advantech Co., Ltd. Information provided in this manual is intended to be accurate and reliable.
Declaration of Conformity CE This product has passed the CE test for environmental specifications when shielded cables are used for external wiring. We recommend the use of shielded cables. FCC Class A Note: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment.
Warnings, Cautions and Notes Warning! Warnings indicate conditions, which if not observed, can cause personal injury. Caution! Cautions are included to help you avoid damaging hardware or losing data, for example, there is a danger of a new battery exploding if it is incorrectly installed. Do not attempt to recharge, force open, or heat the battery. Replace the battery only with the same or equivalent type recommended by the manufacturer. Discard used batteries according to the manufacturer’s instructions.
Safety Instructions 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. Read these safety instructions carefully. Keep this User Manual for later reference. Keep this equipment away from humidity. Put this equipment on a reliable surface during installation. Dropping it or letting it fall may cause damage. All cautions and warnings on the equipment should be noted. Always use caution when handling/operating the computer.
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Glossary ACPI Advanced Configuration and Power Interface AHCI Advanced Host Controller Interface AMC Advanced Mezzanine Card APIC Advanced Programmable Interrupt Controller ATCA Advanced Telecommunications Computing Architecture BI Base Interface BMC Baseboard Management Controller CMC Carrier Management Controller EHCI Enhanced Host Controller Interface FI Fabric Interface FMM Fabric Mezzanine Module FRU Field Replaceable Unit FW Firmware GbE Gigabit Ethernet HPM Hardware Platf
ShMC Shelf Manager Controller SOL Serial Over LAN TCLK Telecom Clock TPM Trusted Platform Module TX Transmit UDIMM Unbuffered DIMMs UHCI Universal Host Controller Interface VLP Very Low Profile XAUI X (means ten) Attachment Unit Interface
Chapter 1 Product Overview This chapter briefly describes the MIC-5332.
1.1 MIC-5332 Overview The MIC-5332 is a dual socket AdvancedTCA blade based on the Intel® Xeon E5-2600 series EP processors and C600 PCH (codename Patsburg). The MIC-5332 enables the highest performance available in an ATCA form factor with up to 16-cores and 32-threads of processing power, fast PCI Express gen 3 lanes running at up to 8Gbps, and best in class virtualization support.
Mirroring.(please refer to chapter 4) Advantech IPMI firmware has been tested for CP-TA compliance using the Polaris Networks ATCA Test Suite. The MIC-5332 supports hot-swappable RTMs such as the RTM-5104 for High Availability (HA) needs, rear I/O and dual SAS storage with RAID as well as an optional FMM. Please contact Advantech for more information on available RTMs.
1.2 Block Diagram The hardware implementation is shown in the following block diagram. Refer to Table 1.1 (next page) for the detailed product technical specification. : Option Figure 1.
1.3 Product Configurations Model Name Configurations MIC-5332SA1-P1E MIC-5332 RJ45 version with dual Intel® Xeon® E5-2648L CPU MIC-5332SA1-P2E MIC-5332 RJ45 version with dual Intel® Xeon® E5-2658 CPU MIC-5332SB1-P1E MIC-5332 SFP version with dual Intel® Xeon® E5-2648L CPU MIC-5332SB1-P2E MIC-5332 SFP version with dual Intel® Xeon® E5-2658 CPU Table 1.1 MIC-5332 Configurations Note: Support max 256GB using 8 pieces of 32GB DDR3-1600 VLP DIMM modules. 1.
Chapter 2 Board Features This chapter describes the MIC-5332 hardware features.
2.1 Technical Data CPU Dual Intel® Xeon® E5-2648L/E5-2658 8-core processors(1) Max. Speed 2.1GHz Processor System Chipset BIOS Dual 64-Mbit BIOS firmware flashes with AMI UEFI based BIOS QPI 8.0 GT/s Technology Memory Intel® C604 Four channel DDR3 1066/1333/1600MHz SDRAM (72-bit ECC Un-/ Registered), LR DIMM support Max.
Environment Operating Non-operating Temperature 0 ~ 55° C (32 ~ 131° F) - 40 ~ 70° C (-40 ~ 158° F) Humidity 5 to 93%@40°C (non 95% @ 40° C (non-condensing) condensing) Shock 4 G each axis 20 G each axis Vibration (5~500Hz) 0.5 Grms 2.16 Grms, 30 mins each axis ETSI EN300019-2-1 Class1.2, EN300019-2-2 Class 2.3, ETSI Environment Compliance EN300019-2-3 Class 3.1E, Designed to meet GR63-CORE PICMG 3.0 R3.0, 3.1 R1.0, HPM.1 Safety CE mark (EN60950-2001), UL60950-1/CSAC22.
The E5 series Xeon processors support cache memory as listed below: A 32-KB instruction and 32-KB data first-level cache (L1) for each core. A 256-KB shared instruction/data mid-level (L2) cache for each core. Up to 20 MB last level cache (LLC): up to 2.5 MB per core instruction/data last level cache (LLC), shared among all cores. 2.2.2 Platform Controller Hub (PCH) An Intel® C604 provides the peripheral connection in the Intel® Sandy Bridge platform.
PCIe hot swap is not supported for graphic controllers (e.g. FMM-5002E) installed on a RTM. 2.2.5 Redundant BIOS Flash The MIC-5332 has two SPI flash devices for storing redundant x86 firmware (BIOS, BIOS configuration, etc.). The integrated management controller (IPMC) controls which flash device is active. Failover and rollback operations between the flash devices are compliant to HPM.1.
Table 2.4 SATA Port Configuration on the MIC-5332 The MIC-5332 is also able to support SAS devices. 4 SAS 2.0 channels are reserved for SAS or SATA devices on RTM boards. For details, please see table 2.5. Port No. Speed Description 0 1 3Gbps 2 Supports extended SAS/SATA devices on RTM (connected to Zone 3) 3 Table 2.5 SAS Port Configuration on the MIC-5332 2.2.
MIC-5332 are listed as table 2.7. Figure 2.2 DIMM slots on the MIC-5332 DIMM Type Size RDIMMs UDIMMs 2GB, 4GB, 8GB, 16GB and 2GB, 4GB and 8GB 32GB Speed Ranks LRDIMMs 8GB, 16GB and 32GB 1066 / 1333 / 1600 SR, DR, QR (only for 1066 / 1333 SR, DR 1066/1333) QR Table 2.7: Supported DIMM Configurations 2.
Mirrored Channel Mode In Mirrored Channel Mode, the memory contents are mirrored between Channel 0 and Channel 2 and also between Channel 1 and Channel 3. As a result of the mirroring, the total physical memory available to the system is half of what is populated. Mirrored Channel Mode requires that Channel 0 and Channel 2, and Channel 1 and Channel 3 must be populated identically with regards to size and organization.
The MIC-5332 also supports PXE boot and SoL (Serial-over-LAN) over the Base Interface channels. PXE boot can be enabled “Launch PXE OpROM” through the BIOS setup menu (see Section 5.4., Advanced BIOS Features Setup). Information about PXE expansion ROM configuration is also provided in this section. The Intel i350 controller supports side-band functionality. This side-band interface (NC-SI) is used by the IPMC to establish LAN sessions, to enable RMCP/RMCP+ based communication to the management part.
Intel® i350-AM4 Copper or 10/100/1000 Mb/s I/O Interface Front Panel Ports 2, 3 Fiber Intel® 82579 Copper 9 10/100/1000 Mb/s Table 2.8: Ethernet Interface Link Speed Configuration 2.5 Zone 3 Interface (RTM) The MIC-5332 supports the following connectivity to an optional RTM through the zone 3 interface (please refer to the Appendix D, Zone3 interface (RTM) pin-out): 1x PCI Express x16 1x PCI Express x4 4x USB 2.
The FMM board is generally used to provide an option to expand the feature sets, both for the main board and RTM board. It is managed by the main board’s IPMC or RTM board’s MMC, but does not support the hot-swap function. Customers may request a customized FMM (please contact your Advantech representative) or choose from the following Advantech FMM-5000 options. For detailed specifications, please refer to table 2.10. ).
Chapter 3 Installation This chapter describes the procedure to install the MIC-5332 into a chassis. Peripherals (DIMMs, SSD) installation, jumper setting and LED definition are also described here.
3.1 Processor The MIC-5332 is shipped with two CPUs and heat sinks installed. Please do not attempt to remove the heat sinks, or the cooling performance will be affected. Tampering with the heat sinks will result in loss of warranty. 3.2 Memory 3.2.1 Requirement As described in Section 2.3, DDR3 DIMMs, the MIC-5332 supports 8 x DDR3 VLP (very low-profile, 0.72inch; 18.29mm) un-buffered/registered ECC SDRAM DIMMs.
1. Open the ejector on the empty DIMM socket where you want to install the DIMM. 2. Insert the memory module into the empty slot. Please align the notches on the module with the socket keys. 3. Push the module into socket until the ejectors firmly lock. 4. Repeat steps 1~3 for the remaining modules to be populated. 5. Install the MIC-5332 into the chassis and boot the board, checking if all the memory information shown in BIOS menu is correct. (See Section 3.3, Console Terminal Setup and Section 3.
connected and the user enters any character, the multiplexer will then switch the output to this interface as this is the latest request. The previous RJ45 link will consequently become disconnected. RJ45 miniUSB SoL UART MUX UART1 Zone3 UART2 Step1. User establishes the console link through any available output (e.g.
RJ45 miniUSB SoL UART MUX UART1 Zone3 UART2 Step2. When the user plugs another console cable into the MIC-5332, (e.g.
RJ45 X miniUSB SoL UART MUX UART1 Zone3 UART2 Step3. The original link (RJ-45) becomes disconnected Figure 3.2 UART Multiplexer Switching Mechanism RJ45 (COM1) For a terminal PC to connect to the console function on the MIC-5322 with a RJ45 to DB9 cable, no additional driver is needed.
convert data traffic between USB and UART formats. This chip includes a complete USB 2.0 full-speed function controller, bridge control logic, and a UART interface with transmit/receive buffers and modem handshake signals. For a terminal PC to connect to the console function on the MIC-5332 with a mini-USB to USB cable, the CP2102 driver is available for download from Silicon Labs® website (hyperlink below), and must be installed on the terminal PC. The PC can, for example, run a Linux 2.4 or 2.
3.3.3 PuTTY Configuration Assuming both the CP2102 driver and PuTTY have been installed successfully on the terminal PC with Microsoft Windows, the user can check the COM port (UART) number under “COM and LPT” in the “Device Manager”, which can be accessed by entering the “Control Panel” followed by opening up “System” and then “Hardware”. Let us assume the CP210x USB to UART Bridge Controller has been assigned with “COM12”, you can open up PuTTY and begin the configuration as shown below.
Figure 3.3b PuTTY Configurations If the connection is successful and the user enters BIOS setup menu, upon boot the MIC-5332 BIOS setup menu will be displayed on the PuTTY screen. Figure 3.
3.4 Installing the MIC-5332 3.4.1 MIC-5332 To install MIC-5332 into the chassis: 1. Leave the ejector handles in the open position. 2. Choose a node slot in chassis, and align the PCB edge to the card guide rail.* 3. Carefully slide the MIC-5332 into the system until the connector contacts start to mate into the backplane. Make sure the front panel alignment pin falls into the receptacle. Retaining Thumbscrews Figure 3.5 Alignment pin slides into the receptacle 4.
Note: Regarding the slot information, please refer to the backplane/chassis manual The MIC-5332 also supports hot-swap, i.e. no need to turn off the chassis power before installing the board. To extract the MIC-5332 from the chassis: 1. Unlock the ejector handle at the bottom side, next to the FMM bay. 2. The extraction request will be delivered to the IPMC. The IPMC will perform a graceful shutdown of the ACPI aware operating system.
FMM installed. Mounting instructions are still provided here to support customer development as well as inhouse RMA and repair. For installation of the FMM, please follow the below procedures: 1. Locate the FMM site on the blade (refer to figure 3.9) and make sure the module and the carrier connectors are aligned. Insert the FMM module until the connector is firmly seated in the socket. 2. Install the screws (refer to figure 3.10), and power on the MIC-5332 to make sure the installation is completed. 3.
SSD Bracket FMM Module Figure 3.8 MIC-5332 w/ FMM module and SSD Bracket locations Figure 3.
Figure 3.10 Install the screws 3.4.3 RTM (Optional) For installation of the RTM, please refer to the RTM user manual. Please make sure that the RTM used in conjunction with the MIC-5332 is compliant. Please contact your Advantech representative to obtain a list of compliant RTMs (the current compliant RTM at the time of publication is the RTM-5104). 3.4.4 Storage (Optional) Solid State Drive (SSD) or CFast cards are available to be installed on the MIC-5332. The MIC-5332 can support one 2.
For details, please contact your Advantech representative to obtain further support. Retaining Thumbscrews FI Channel 1/2 Status LEDs Handle (Top side) BI Channel1/2 Status LEDs SAS Status LEDs OOS LED Dual Color User LEDs Health LED Button2 (Reserved) Button1 (Reserved) USB2 USB1 COM2 (miniUSB) COM1 (RJ45) LAN3 (RJ45) LAN2 (SFP or RJ45) LAN1 (SFP or RJ45) Hot Swap LED FMM Bay Handle (Bottom side) Retaining Thumbscrews Figure 3.9 MIC-5332 Front Panel Configuration 3.4.
Display Status Bright … Blink Off Table 3.
Note: FI channel 3 and 4 support is optional and only active when populating with the FMM-5001BE on the FMM site of the MIC-5332. 3.4.7 Jumper Settings This section describes the jumpers on the MIC-5332 for reference. In normal operation, users are not to access or modify jumpers.
JP1 JP6 JP5 Figure 3.
Chapter 4 Hardware Management This chapter describes the IPMC firmware features.
4.1 Overview A complete management mechanism is strength of AdvancedTCA. An on board IPMC (Intelligent Platform Management Controller) is in charge of collecting board information (e.g. sensor events, health status, hot swap, etc.), log events to a repository, and forwards them to the ShMC (Shelf Manager Controller). The shelf manager will take actions based on these messages as needed. 4.
Figure 4.1 IPMC Interface Block Diagram 4.2.1.1 IPMB-0 Interface The IPMB0 interface is the communication path between the ShMC and IPMC through Zone 1. Two–way redundant IPMB-0 channels (IPMB0-A and IPMB0-B) provide immunity against failures of one of IPMB-0 channels. For a request received over IPMB0-A, the response will be sent over IPMB0-B. Any requests that time out are retried on the redundant IPMB bus.
Note: The IPMC firmware provides an OEM IPMI command to allow users to switch the IMPC/FPGA connected NC-SI interface between the front panel LAN IO and the Base interface LAN controllers and also to select between the 2 IO and BI connections.
LAN channel selection priority setting list: 0 = The first channel that links up, gets the NC-SI connection to the BMC. 1 = Channel 1 is the preferred port if it is up, otherwise use channel 2 if it is up. 2 = Channel 2 is the preferred port if it is up, otherwise use channel 1 if it is up. 3 = Channel 1 is the only allowed port, always use it, never change to channel 2. 4 = Channel 2 is the only allowed port, always use it, never change to channel 1.
Field description Board information Format version 0x01 Board area length (calculated) Language code 0x19(English) Manufacturer date/time (Based on manufacturing date) Board manufacturer type/length 0xC9 Board manufacturer Advantech Board product name type/length 0xC8 Board product name MIC-5332 Board serial number type/length 0xCA Board serial number (10 characters, written during manufacturing) Board part number type/length 0xC8 Board part number MIC-5332 FRU file ID type/length
Assert Tag type/length 0xC0 Assert Tag (unused) FRU File ID type/length 0xCC FRU File ID frudata.xml Custom product info area fields (unused) C1h (no more info fields) 0xC1 00h (any remaining unused space) (unused) Product area checksum (calculated) Table 4.2 Product Information Area 4.3 Sensors The IPMC Firmware supports the following hardware sensors monitoring: onboard voltage sensors, onboard analog/discrete temperature sensors and power input module sensors.
Sensor Name Description FRU Device Locator IPMI FRU Device Locator HOTSWAP PICMG Frontboard Hotswap sensor HS_RTM PICMG RTM Hotswap sensor BMC_WATCHDOG IPMI Watchdog 2 sensor FW_PROGRESS IPMI FW Progress sensor VERSION_CHANGE IPMI Version Change sensor IPMB_0 PICMG IPMB-0 status sensor VR_HOT Discrete sensor Voltage regulator Status PROC_HOT Discrete sensor Processor HOT status THERM_TRIP Discrete sensor CPU 0/1 Thermal Trip BOARD_POWER Board Power sensor V48-CUR Threshold sensor DC
CPU1_CORE-VOL Threshold sensor CPU-1 Core Voltage CPU1_1_80-VOL Threshold sensor CPU-1 1.80V DDR_AB-VOL Threshold sensor DDR Voltage 1.5V DDR_CD-VOL Threshold sensor DDR Voltage 1.5V DDR_EF-VOL Threshold sensor DDR Voltage 1.5V DDR_GH-VOL Threshold sensor DDR Voltage 1.
Sensor Name Nomina LNR LCR LNC UNC UCR UNR l Value V48-CUR range - - - 7.6 8.5 9.5 HU-CAP-VOL 65 0 - - 78 83 88 V48_A-VOL 48.0 36.0 38.0 40.0 70.0 75.0 80.0 V48_B-VOL 48.0 36.0 38.0 40.0 70.0 75.0 80.0 BAT_3_0-VOL 3.00 2.70 2.80 2.90 3.45 3.65 3.80 MAN_3_3-VOL 3.30 2.80 3.00 3.15 3.45 3.60 3.80 VSB_5_0_VOL 5.00 4.30 4.50 4.65 5.35 5.50 5.70 PAY_3_3-VOL 3.30 2.80 3.00 3.13 3.50 3.60 3.80 PAY_5_0-VOL 5.00 4.30 4.50 4.75 5.25 5.
area and the other one is located in the air outlet area. Temperatures of the DIMM air inlet and CPU are monitored by the CPU internal digital sensor, and are read by the NCT7904D (with ±1℃ accuracy.). Digital error and exception events are supported by the FPGA, such as Thermal Trip, Processor Hot, DDR3 Thermal Event, and others. The management block may log thermal events and forward event messages to the Shelf Manager, or activate protection.
4.3.3 Discrete sensors 4.3.3.1 IPMC Device Locator Each IPMC provides a PICMG compliant FRU device locator for the subsystem. This record is used to hold location and type information of the IPMC. 4.3.3.2 Mezzanine Module Device Locator The FRU device locator for each Add-In card is also placed in the front board sensor data repository. 4.3.3.3 FRU Hotswap Sensor (Front blade) Each IPMC contains a PICMG compliant Hot Swap sensor inside it’s sensor data repository. 4.3.3.
4.3.3.8 VR HOT Sensor The IPMC contains a sensor to monitor the state of the voltage regulators on each subsystem. The sensor is implemented as a discrete OEM sensor. The single bits can be seen in following table. Bit 7 6 5 4 3 2 1 0 Description - - - - - - VR VR CPU 1 CPU 0 HOT HOT Table4.7: Voltage Regulator Sensor Bits 4.3.4 Integrity Sensor The Integrity Sensor is an OEM sensor per IPMI specification..
BIOS IPMC FRU RTC Update Successful 0x03 0x00 Update Timeout 0x03 0x04 Update Aborted 0x03 0x02 Flash 0 boot Failed 0x03 0x29 Flash 1 boot Failed 0x03 0x31 Common header CKS Error 0x08 0x3B Internal area CKS Error 0x08 0x43 Chassis info area CKS Error 0x08 0x4B Board info area CKS Error 0x08 0x53 Product info area CKS Error 0x08 0x5B Multi record area CKS Error 0x08 0x63 Time sync with ShMM Successful 0x09 0x68 Time sync with ShMM Failed 0x09 0x69 Table
If the BMC watchdog is enabled again for OS load supervision, the user needs to make sure the running OS will reset or disable the BMC watchdog afterwards. If not, the IPMC will reset the payload as the timeout action. The default timeout period for the BMC watchdog used as the BIOS POST timer and OS load supervision is 60 seconds. This setting can be changed through the BIOS setup menu. Please refer to Section 5.6.3, Watchdog Timer Configuration.
console communication with the payload over a LAN interface (See Section 4.2.1.4, NC-SI Interface). The SoL function is available for I/O LAN (LAN1 & LAN2) and the Base Interface, but not simultaneously.
3. Choose a proper connection (LAN, KCS, or IPMB) to the MIC-5332. Taking LAN for example, connect theFront Panel IO GbE-LAN RJ-45 port (LAN1 or LAN2) to the LAN port on a PC via an Ethernet cable. 4. Turn on the MIC-5332. 5. Use a command line on the remote PC, then move to the directory where IPMItool is located. 6. IPMItool is ready for use now. For Linux users: 1. Make sure the IPMI driver has been mounted. (The built-in IPMI driver in current Linux kernel is compatible with MIC-5332) 2.
Set IP Address of the Static LAN Interface Command Line Syntax: ipmitool -I lan -H -A lan set -I lan Specifies that Ethernet is used as interface for communications with the IPMC -H Default IP address of LAN interface 192.168.1.1 -A Authentication type (depending on supported types by the Shelf Manager: NONE, PASSWORD, MD2, MD5 or OEM), default: NONE Default used channel: 5 0: IPMB-0 1: Serial 2.
<1.1> Supported LAN interfaces Four of MIC-5332’s Ethernet interfaces can be used for Serial over LAN: ‐ Base interface channel 1/2 ‐ I/O interfaces 1/2 The LAN controller for NCSI is powered by management power and provides access to the management part over LAN even if payload is powered off. <1.2> LAN Controller and UART MUX configuration The LAN and UART configuration of the BMC is flexible and allows different configurations.
To get an overview of all possible commands within an IPMItool command group, please use the single keywords (e.g. “lan”, “user” or “sol”) only. <2.1> LAN Commands - lan print [channel number] Get the LAN configuration parameters for a given channel.
<2.2> User Commands - user list Get the list of all supported users. [root@localhost ~]# ipmitool user list ID Name Callin Link Auth IPMI Msg Channel Priv Limit 1 true true CALLBACK true CALLBACK 2 callback true 3 user true true true USER 4 operator true true true OPERATOR 5 administrator true true true true true ADMINISTRATOR - user set name [username] This command can be used to change the user name.
Command Line Syntax: -I lan Specifies Ethernet interface -H IP address assigned to the IPMC -U User account, default “administrator” -P Password used with specified user account (default password for user “administrator” is “advantech”) <3.1> SOL Parameter Commands - sol info [channel number] Read out the SOL configuration parameters for a given channel.
# ipmitool -I lanplus -U -P sol set SOL set parameters and values: set-in-progress set-complete | set-in-progress | commit-write enabled true | false force-encryption true | false force-authentication true | false privilege-level user | operator | admin | oem character-accumulate-level character-send-threshold N retry-count N retry-interval non-volatile-bit-rate serial | 9.6 | 19.2 | 38.4 | 57.6 | 115.
replying the predefined value, e.g. 300W to the shelf manager, the MIC-5332 IPMC uses an intelligent mechanism to auto-detect current CPU type and the amount and size of the DIMMs, the RTM power draw and the FMM power draw thus calculating and reporting a power value, which is representing the real power requirements of the current blade configuration. Note: The user may disable this function via Advantech’s IPMI OEM command: “ipmitool raw 0x2e 0x40 0x39 0x28 0x00 0x06 0x00 0x00”. 4.
Command Line Syntax: “Read MAC address” OEM IPMI command Request Data b8 00 Response Data <6 bytes MAC address> Net function 0x2E / 0x2F (OEM) 0xe2 Advantech IANA ID = 0x39 28 00 0x00 for Fabric Interface Channel 0 0x01 for Fabric Interface Channel 1 0x02 for Base Interface Channel 0 0x03 for Base Interface Channel 1 0x04 for Front Panel IO Channel 0 0x05 for Front Panel IO Channel 1 0x06 for PCH IO
Figure 4.4 Real Time Clock Synchronization Overview From IPMC’s point of view are two more participants in an ATCA System, which maintain their own time, because they implement a separate Real-Time-Clock. These are the Shelf Manager and the on-board payload. The IPMC firmware has implemented a RTC synchronization feature, which allows configuring the RTC synchronization between Shelf Manager, IPMC and payload according to the need of each user.
Chapter 5 AMI APTIO BIOS Setup This chapter describes how to configure the AMI APTIO BIOS (UEFI BIOS).
5.1 Introduction The AMI BIOS has been customized and integrated into many industrial and embedded motherboards for over a decade. In order to extend the features on the Intel Sandy Bridge Platform, Advantech implement the latest AMI APTIO BIOS into the MIC-5332 to enhance its operating performance. This section describes the AMI APTIO BIOS, UEFI compliant, which has been specifically adapted to the MIC-5332.
showing basic BIOS and blade information.Press or and users will immediately be allowed to enter Setup. Figure 5.2 Press or to run setup 5.3 Main Setup When users first enter the BIOS Setup Utility, users will enter the Main setup screen. Users can always return to the Main setup screen by selecting the Main tab. Two main setup options are described in this section. The main BIOS setup screen is shown below. The main BIOS setup menu screen has two main frames.
IPMC Version Display only Show IPMC version FPGA Version Display only Show FPGA version SPI Active Display only Show the active SPI Time Zone GMT +00:00 Set the time zone System Language English Set the system language System Date MM/DD/YY Set the system date System Time HH:MM:SS Set the system time Access Level Display only Default as Administrator Table 5.1 BIOS Menu: Main 5.3.1 Time Zone and System Language Use this option to change the time zone and system language.
Figure 5.
5.4.1 PCI Subsystem Settings Figure 5.4 PCI Subsystem Settings Feature Default PCI Bus Driver Version Display only PCI ROM Priority Description Show current PCI bus driver version EFI In case of multiple Option ROMs (Legacy and Compatible EFI Compatible), specifies what PCI Option ROM ROM to launch. Enables or Disables 64bit capable Devices to Above 4G Decoding Disabled be Decoded in Above 4G Address Space (Only if System Supports 64 bit PCI Decoding).
5.4.2 ACPI Settings Figure 5.5 ACPI Settings Feature Default Enable ACPI Auto Conf Disabled Description Enables or Disables BIOS ACPI Auto Configuration. Enables or Disables System ability to Hibernate Enable Hibernation Enabled (OS/S4 Sleep State). This option may be not effective with some OS. ACPI Sleep State Lock Legacy Resources S3 (Suspend to RAM) Disabled Select the highest ACPI sleep state the system will enter when the SUSPEND button is pressed.
Figure 5.6 Trusted Computing Feature Default Description Enables or Disables BIOS support for security Security Device Sup Enabled device. O.S. will not show Security Device. TCG EFI protocol and INT1A interface will not be available. Enable/Disable Security Device. NOTE: Your TPM State Disabled Computer will reboot during restart in order to change State of the Device. Pending Operation Display Only Show current pending operation item.
Figure 5.7 WHEA Configuration 5.4.5 CPU Configuration Figure 5.
64-bit Display Only Show if the current CPU supports 64-bit or not Enabled for Windows XP and Linux (OS optimized for HT Technology) and Disabled Hyper-threading Enabled for other OS (OS Hyper-Threading not optimized Technology). for When Disabled only one. Active Processor Core All Limit CPUID Maximum Disabled Number of cores to enable in each processor package.
User can enable or disable the runtime error logging support via a sub option of the advanced setting (default is disabled). Figure 5.9 Runtime Error Logging 5.4.7 SATA Configuration Figure 5.
Feature Default Description SATA Port0 Display only SATA Port1 Display only SATA Port2 Display only Show current SATA devices in use on the SATA Port3 Display only MIC-5332 SATA Port4 Display only SATA Port5 Display only SATA Mode AHCI Mode (1) IDE Mode. (2) AHCI Mode. (3) RAID Mode. Enabled Aggressive Link Power Management Support. Aggressive Link Power Table 5.7 SATA Configuration The MIC-5332 supports total 6 SATA devices (details, please refer to section 2.2.6).
The MIC-5332 supports USB Plug & Play, PnP. That is, users can find all USB devices which are plugged on the MIC-5332. They can configure the parameters to enhance the USB device performance, such as mass storage devices. Figure 5.12 USB Configuration Feature Default Description Enables Legacy USB support. AUTO option Legacy USB Support Enabled disables legacy support if no USB devices are connected. Disable option will keep USB devices available only for EFI application.
5.4.10 UART MUX Configuration The MIC-5332 supports two UART channels. Users can select the different methods (SoL, FP-RJ45, FP-USB, RTM0 and RTM1) to access the UART channel. The default setting for channel1 is FP-USB, and FP-RJ45 for channel2. Users can also decide to open all available methods to access the UART channel. Figure 5.13 UART MUX Configuration 5.4.11 Serial Port Console Redirection The MIC-5332 has two COM ports that are integrated on the front panel.
The settings specify how the host computer Console Redirection Settings Submenu and the remote computer (which the user is using) will exchange data. Both computers should have the same or compatible settings. Table 5.9 Serial Port Console Redirection Figure 5.14 Serial Port Console Redirection 5.4.12 Network Stack Users can enable or disable the network stack (PXe and UEFI) via this submenu (default is disable Link).
Figure 5.15 Network Stack 5.4.13 iSCSI This function allows users to give a worldwide unique name for the iSCSI initiator. Figure 5.16 iSCSI Initiator 5.4.14 Main Configuration Page The MIC-5332 supports five MACs (four from the Intel i350, one from the PCH). Users can configure legacy boot protocol, link speed and Wake On LAN for each of them.
Also, users can find the corresponding MAC address for each LAN here. Figure 5.17 Main Configuration Page 5.5 Chipset Setup Select the chipset tab from the MIC-5332 setup screen to enter the Chipset Setup screen. Users can configure the parameters of north bridge (CPU), south bridge (PCH) and ME system (display only), respectively.
Figure 5.16 Chipset Configuration 5.5.1 North Bridge Users can set up all parameters related to the IOH function in the North Bridge page. Moreover, the MIC-5332 BIOS allows users to configure the PCIe link speed (gen1, gen2 or gen3) and its functions visible (x16, x8x8, x8x4x4, x4x4x8 or x4x4x4x4) in the IOH configuration submenu. Also, the Sandy Bridge CPU supports two QPI channels. Users can configure the related settings in the QPI configuration submenu.
Figure 5.17 North Bridge Configuration 5.5.2 South Bridge Users can set up all parameters related to the PCH function in the South Bridge page. Also, users can configure (to enable or disable) eight USB 2.0 channels supported on the MIC-5332 in this page. Feature Name Stepping Default Description Display only Display only Support for PCH Compatibility Revision ID PCH Compatibility RID Disabled SMBus Controller Enabled Enabled/Disabled SMBus Controller.
Disable SCU devices Disabled Enable/Disable Patsburg SCU Devices. Onboard SAS Oprom Disabled Onboard SATA RAID Opr Enabled High Precision Timer Enabled Enable/Disable the High Precision Event Timer. USB Configuration Submenu Advanced USB Configuration Enable/Disable onboard SAS Option rom if Launch Storage OpROM is enabled. Enable/Disable onboard SATA RAID Option rom if Launch Storage OpROM is enabled. Table 5.11 South Bridge Configuration Figure 5.
5.6 Server Management (Mgmt) Setup Users can configure the watchdog timer both for the FRB-2 and OS Wtd in the server mgmt page. For details of the BMC self test log and system event log, users can decide to enable the function to record the logs, or erase the logs through BMC self test log submenu, or the system event log submenu. Also, users can check the FRU information via the submenu of view FRU information (display only). Figure 5.
BMC self test log Submenu System Event Log Submenu View FRU information Display Only Logs the report returned by the BMC self test command. Press to change the SEL event log configuration. Press to view FRU information. Table 5.12 Server Mgmt Configuration 5.7 Boot Setup Users can configure the system boot priority settings via the boot page.
Enables or disables boot with an initialization of a minimal set of devices Fast Boot Disabled required to launch active boot option. Has no effect for BBS boot option. CSM16 Module Version Display Only Shows the current version in use. Option ROM Messages Force BIOS Set display mode for Option ROM. Interrupt 19 Capture Boot Option Hard Drive BBS Priorities Immediate User Defined Submenu Enabled: Allows Option ROMs to trap Int 19. Sets the system boot order.
If ONLY the Administrator's password is set, then this only limits access to Setup and is only asked for when entering Setup. If ONLY the User's password is set, then this is a power on password and must be entered to boot or enter Setup. In Setup the User will have Administrator rights. The password length must be in the following range: Minimum length: 3 Maximum length: 20 5.9 Save & Exit Option The MIC-5332 BIOS allows users to store BIOS configuration results as “User Defaults.
Restore Defaults Restore/Load Default values for all the setup options. Save as User Defaults Save the changes done so far as User Defaults. Restores User Defaults Restore the User Defaults to all the setup options. Table 5.
Chapter 6 Firmware Upgrade This chapter describes how to update the IPMC FW, FPGA and BIOS for the MIC-5332.
6.1 HPM.1 Upgrade Functionality All firmware updates/upgrades (IPMC firmware, FPGA configuration and BIOS SPI Flash) can be performed through HPM.1 over IPMI. Please follow the procedures described in the following sections. 6.2 IPMItool Before upgrading, users need to prepare an update utility called “IPMItool” or any other HPM.1 compliant upgrade agent. For simplicity, the remaining descriptions reference IPMITool. HPM.
[root@localhost ~]#ipmitool hpm upgrade mic5332_standard_hpm_fw_00_46.img PICMG HPM.1 Upgrade Agent 1.0.2: Validating firmware image integrity...OK Performing preparation stage...
6.3.2 Activate HPM FW image Although the new IPMC FW is successfully downloaded to the board (called “deferred” version), it needs to be activated before it will be functional. Use following HPM.1 command: [root@localhost ~]# ipmitool hpm activate PICMG HPM.1 Upgrade Agent 1.0.2: Waiting firmware activation...OK During the FW update the front panel FRU LED’s 1 and 2 (red OOS and green payload LED) are flashing! This procedure needs around 30 seconds to finalize the update.
[root@localhost ~]#ipmitool hpm upgrade mic5332_standard_hpm_fpga_02_14.img PICMG HPM.1 Upgrade Agent 1.0.2: Validating firmware image integrity...OK Performing preparation stage...
6.4.2 Activate HPM FPGA image Although the new FPGA is successfully downloaded to the board (called “deferred” version), it needs to be activated before it will be functional. Use following HPM.1 command: [root@localhost ~]# $ ipmitool hpm activate PICMG HPM.1 Upgrade Agent 1.0.2: 6.4.3 Payload Reset In order to activate the new FPGA image a payload reset is required. (*) Component requires Payload Cold Reset The payload reset can be performed through different ways.
6.4.4 Verify successful Upgrade To verify the update process the hpm check of the IPMItool can be used again. Now the FPGA Backup Version should be the former active version, and the active version should be the version of the upload file. [root@localhost ~]# ipmitool hpm check PICMG HPM.1 Upgrade Agent 1.0.
6.5.1 Upload new BIOS image Type IPMItool HPM.1 upgrade command and select the new BIOS image. [root@localhost ~]# ipmitool hpm upgrade mic5332_standard_hpm_bios_00_23.img PICMG HPM.1 Upgrade Agent 1.0.2: Validating firmware image integrity...OK Performing preparation stage...
[root@localhost ~]# $ ipmitool hpm activate PICMG HPM.1 Upgrade Agent 1.0.2: 6.5.3 Payload Reset In order to activate the new BIOS image a payload reset is required. (*) Component requires Payload Cold Reset The payload reset can be performed through different ways. If the user is working on the OS via KCS a linux “reboot”,”poweroff” or “halt” will activate the new BIOS image.
[root@localhost ~]# ipmitool hpm check PICMG HPM.1 Upgrade Agent 1.0.2: -------Target Information------Device Id : 0x22 Device Revision : 0x81 Product Id : 0x5332 Manufacturer Id : 0x2839 (Advantech) --------------------------------|ID | Name | | | Active| Backup| | Versions | --------------------------------- 6.6 NVRAM Upgrade In contrast to the BIOS image update, the setting update image is not directly written to any of the BIOS SPI flashes.
[root@localhost ~]# ipmitool raw 0x2E 0x40 0x39 0x28 0x00 0x03 0x01
6.6.2 Upload new NVRAM image Type IPMItool HPM.1 upgrade command and select the new NVRAM image. [root@localhost ~]# ipmitool hpm upgrade mic5332_standard_hpm_bios_00_05.img PICMG HPM.1 Upgrade Agent 1.0.2: Validating firmware image integrity...OK Performing preparation stage...
6.6.4 Payload Reset In order to activate the new NVRAM image a payload reset is required. (*) Component requires Payload Cold Reset The payload reset can be performed through different ways. If the user is working on the OS via KCS a linux “reboot”,”poweroff” or “halt” will activate the new NVRAM image. If the user accesses the BMC through other interfaces (LAN/IPMB) a deactivation and activation cycle is needed, in order to update the NVRAM.
Appendix A IPMI/PICMG Command Subset Supported by IPMC
IPM Device “Global” Commands Command IPMI Spec Ref NetFn CMD IPMI / PICMG3.0 / AMC2.0 Requirement Get Device ID 20.1 App 01h Mandatory Cold Reset 20.2 App 02h Optional Warm Reset 20.3 App 03h Optional Get Self Test Results 20.4 App 04h Mandatory Get Device GUID 20.8 App 08h Optional Broadcast “Get Device ID 20.9 App 01h Mandatory NetFn CMD BMC Watchdog Timer Commands Command IPMI Spec Ref IPMI / PICMG3.0 / AMC2.0 Requirement Reset Watchdog Timer 27.
Set User Access 22.26 App 43h Optional Get User Access 22.27 App 44h Optional Set User Name 22.28 App 45h Optional Get User Name 22.29 App 46h Optional Set User Password 22.30 App 47h Optional Activate Payload 24.1 App 48h None Deactivate Payload 24.2 App 49h None Set User Payload Access 24.6 App 4Ch None Get User Payload Access 24.7 App 4Dh None Get Channel Payload Support 24.8 App 4Eh None Get Channel Payload Version 24.
Get Sensor Reading 35.14 S/E 2Dh Mandatory Get Sensor Type 35.16 S/E 2Fh Optional NetFn CMD FRU Device Commands Command IPMI Spec Ref IPMI / PICMG3.0 / AMC2.0 Requirement Get FRU Inventory Area Info 34.1 Storage 10h Mandatory Read FRU Data 34.2 Storage 11h Mandatory Write FRU Data 34.3 Storage 12h Mandatory NetFn CMD SEL Device Commands Command IPMI Spec Ref IPMI / PICMG3.0 / AMC2.0 Requirement Get SEL Info 31.2 Storage 40h Mandatory Reserve SEL 31.
AdvancedTCA® Commands Command PICMG® 3.0 Table NetFn CMD IPMI / PICMG3.0 / AMC2.
Advantech OEM commands Advantech management solutions support extended OEM IPMI command sets, based on the IPMI defined OEM/Group Network Function (NetFn) Codes 2Eh, 2Fh. The first three data bytes of IPMI requests and responses under the OEM/Group Network Function explicitly identify the OEM vendor that specifies the command functionality.
A.2.1 LAN controller interface selection The MMC firmware provides an OEM IPMI command to allow users to switch the MMC connected NC-SI interface between one front panel LAN IO RJ-45 connector and the Base interface. These commands can be used to read out the actual selected IPMI-over-LAN / Serial-over-LAN interface and to change the selection.
4 = Channel 2 is the only allowed port, always use it, never change to channel 1. The NC-SI LAN controller channel setting will be stored permanently (non-volatile EEPROM). The default value is 0. Read LAN channel selection priority: ipmitool raw 0x2e 0x41 0x39 0x28 0x00 0x04 0x01 Response: 39 28 00 Change LAN channel selection priority: ipmitool raw 0x2e 0x40 0x39 0x28 0x00 0x04 0x01 Response: 39 28 00 A.2.
0x02 Front Panel RJ45 0x03 Front panel mini-USB (default) 0x04 RTM mini-USB 0x05 RTM RJ45 0x0F Automatic mode Table 2: COM1 UART MUX settings COM2 MUX: Setting Connection 0x00 no interface connected, open 0x01 Serial-over-LAN (SOL) 0x02 Front Panel RJ45 0x03 Front panel mini-USB (default) 0x04 RTM mini-USB 0x05 RTM RJ45 Table 3: COM2 UART MUX settings Important Note: The COM1 UART is the main interface with higher priority! There is an important dependency between COM1 and COM2 UARTs
A.3 Read Port 80 (BIOS POST Code) OEM command To be able to read out the actual BIOS boot state via IPMI, the MMC provides an Advantech OEM command to reflect the actual BIOS POST (Port 80) code. ipmitool raw 0x2e 0x80 0x39 0x28 0x00 Response: 39 28 00 A.4 Load NVRAM defaults OEM command The BMC implements an OEM command to be able to load the NVRAM defaults from SW side without the need of extracting the blade and performing any jumper plug and re-plug.
6 PCH MAC 7 IPMC MAC 8..x FMM MAC addresses (if plugged) Table 4: MAC Address mapping table Read MAC Address OEM command: ipmitool raw 0x2e 0xe2 0x39 0x28 0x00 Response: 39 28 00 A.6 Load Default Configuration OEM command Several configurations settings are provided by the IPMC (verify chapter ). To reset all of them to their default values, a single OEM command is available to perform this with only one IPMI command.
Appendix B Zone 1 P10 Pin-out Pin pin name Pin use 1 Reserved No connected 2 Reserved No connected 3 Reserved No connected 4 Reserved No connected 5 HA0 Hardware Address bit 0 6 HA1 Hardware Address bit 1 7 HA2 Hardware Address bit 2 8 HA3 Hardware Address bit 3 9 HA4 Hardware Address bit 4 10 HA5 Hardware Address bit 5 11 HA6 Hardware Address bit 6 12 HA7/P Hardware Address bit 7 13 SCL_A IPMB0-A clock 14 SDA_A IPMB0-A data 15 SCL_B IPMB0-B clock 16 SDA_B I
33 -48V_A -48V input feed A 34 -48V_B -48V input feed B
Appendix C Zone 2 Interface pin-out Zone 2 J20 pin out – Update Channel J20 Pin Row A B C D E F G H 1 N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. 2 Tx4(UP)+ Tx4(UP)‐ Rx4(UP)+ Rx4(UP)‐ 3 Tx2(UP)+ Tx2(UP)‐ Rx2(UP)+ Rx2(UP)‐ Tx3(UP)+ Tx3(UP)‐ Rx3(UP)+ Rx3(UP)‐ 4 Tx0(UP)+ Tx0(UP)‐ Rx0(UP)+ Rx0(UP)‐ Tx1(UP)+ Tx1(UP)‐ Rx1(UP)+ Rx1(UP)‐ 5 N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. 6 N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. 7 N.C. N.C. N.C. N.C. N.C.
Zone 2 J22 pin out – Base Interface and Fabric Interface J22 Pin Row A B C D E F G H 1 N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. 2 N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. 3 N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. 4 N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. 5 N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. 6 N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C.
Zone 2 J23 pin out – Base Interface and Fabric Interface Pin J23 Row A B C D E F G H 1 FI_CH2 Tx2+ FI_CH2 Tx2‐ FI_CH2 Rx2+ FI_CH2 Rx2‐ FI_CH2 Tx3+ FI_CH2 Tx3‐ FI_CH2 Rx3+ FI_CH2 Rx3‐ 2 FI_CH2 Tx0+ FI_CH2 Tx0‐ FI_CH2 Rx0+ FI_CH2 Rx0‐ FI_CH2 Tx1+ FI_CH2 Tx1‐ FI_CH2 Rx1+ FI_CH2 Rx1‐ 3 FI_CH1 Tx2+ FI_CH1 Tx2‐ FI_CH1 Rx2+ FI_CH1 Rx2‐ FI_CH1 Tx3+ FI_CH1 Tx3‐ FI_CH1 Rx3+ FI_CH1 Rx3‐ 4 FI_CH1 Tx0+ FI_CH1 Tx0‐ FI_CH1 Rx0+ FI_CH1 Rx0‐ FI_CH1 Tx1+ FI_CH1 Tx1‐ FI_CH1 Rx1+ FI
Appendix D Zone 3 Interface (RTM) pin-out Zone 3 J31 pin out J31 Row 8 7 Pin M A RTM_+12V RTM_3.
Zone 3 J32 pin out J32 Row Pin M A 8 not connected not connected RTM_USB3 RTM_USB2 7 TCLKD TCLKC TCLKB TCLKA 6 not connected not connected 5 not connected not connected 4 not connected not connected 3 SATA1: RTM_SATA1 SATA1: RTM_SATA0 2 SAS0: RTM_SAS3 SAS0: RTM_SAS2 1 SAS0: RTM_SAS1 SAS0: RTM_SAS0 Zone 3 J34 pin out J34 Row Pin M A PEx16_1: RTM_PE16‐1_0 RX PEx16_1: RTM_PE16‐1_4 RX PEx16_1: RTM_PE16‐1_0 TX PEx16_1: RTM_PE16‐1_4 TX PEx16_1: RTM_PE16‐1_0 PEx16_1: RTM_PE16
3 PEx16_1: RTM_PE16‐1_10 RX PEx16_1: RTM_PE16‐1_14 RX PEx16_1: RTM_PE16‐1_10 TX PEx16_1: RTM_PE16‐1_14 TX 2 PEx16_1: RTM_PE16‐1_3 RX PEx16_1: RTM_PE16‐1_7 RX PEx16_1: RTM_PE16‐1_3 TX PEx16_1: RTM_PE16‐1_7 TX 1 PEx16_1: RTM_PE16‐1_11 RX PEx16_1: RTM_PE16‐1_15 RX PEx16_1: RTM_PE16‐1_11 TX PEx16_1: RTM_PE16‐1_15 TX
Appendix E FMM Interface pin-out F E D C B A 1 NC GND FM_PRSNT# GND NC GND 2 GND NC GND FI3_RX0_P GND PCIE1_TX0_P 3 GND NC GND FI3_RX0_N GND PCIE1_TX0_N 4 NC GND FI3_RX1_P GND PCIE1_TX1_P GND 5 NC GND FI3_RX1_N GND PCIE1_TX1_N GND 6 GND NC GND FI3_RX2_P GND PCIE1_TX2_P 7 GND NC GND FI3_RX2_N GND PCIE1_TX2_N 8 NC GND FI3_RX3_P GND PCIE1_TX3_P GND 9 NC GND FI3_RX3_N GND PCIE1_TX3_N GND 10 GND NC GND FI4_RX0_P GND PCIE1_TX4_P 11 GND NC GND FI
33 FPGA_GPIO_N7 GND PCIE0_RX7_N GND 34 GND NC GND PCIE0_REF_CLK_P GND PCIE1_REF_CLK_P 35 GND NC GND PCIE0_REF_CLK_P GND PCIE1_REF_CLK_P 36 NC GND #FI3_LED_HS GND SAS_SATA0_TX_P GND 37 NC GND #FI3_LED_LS RST# SAS_SATA0_TX_N SAS_SATA0_RX_P 38 GND NC 3.
27 GND FPGA_GPIO_N0 GND PCIE0_TX4_N 28 FPGA_GPIO_P2 GND PCIE0_TX5_P GND 29 FPGA_GPIO_N2 GND PCIE0_TX5_N GND 30 GND FPGA_GPIO_P4 GND PCIE0_TX6_P 31 GND FPGA_GPIO_N4 GND PCIE0_TX6_N 32 FPGA_GPIO_P6 GND PCIE0_TX7_P GND 33 FPGA_GPIO_N6 GND PCIE0_TX7_N GND 34 GND NC GND NC 35 GND NC GND NC 36 NC GND NC GND 37 NC GND NC NC 38 GND USB2_DP GND #FI4_LED_HS 39 USB1_DP USB2_DN 12V #FI4_LED_LS 40 USB1_DN GND 12V GND HPC only LPC
