PCI-1780 8-ch Counter/Timer Card User Manual
Copyright The documentation and the software included with this product are copyrighted 2002 by Advantech Co., Ltd. All rights are reserved. Advantech Co., Ltd. reserves the right to make improvements in the products described in this manual at any time without notice. No part of this manual may be reproduced, copied, translated or transmitted in any form or by any means without the prior written permission of Advantech Co., Ltd. Information provided in this manual is intended to be accurate and reliable.
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Contents 1. INTRODUCTION.................................................................................................................. 1 1.1 FEATURES ....................................................................................................................... 1 1.2 APPLICATIONS ................................................................................................................. 3 1.3 INSTALLATION GUIDE ..............................................................................
C.10 CLEAR INTERRUPT — BASE+44H ............................................................................. 44 C.11 DIGITAL OUTPUT — BASE+48H................................................................................ 44 C.12 DIGITAL INPUT — BASE+48H................................................................................... 44 C.13 BOARD ID — BASE+4EH ......................................................................................... 45 C.
1. Introduction Thank you for buying the Advantech PCI-1780. The PCI-1780 is a general purpose multiple channel counter/timer card for the PCI bus. It targets the AM9513 to implement the counter/timer function by CPLD. It provides eight 16-bit counter channels and 8 digital outputs and 8 digital inputs. The powerful Advantech-designed counter functions fulfill your industrial or laboratory application needs.
Special Shielded Cable for Noise Reduction The PCL-10168 shielded cable is specially designed for the PCI-1780 for reducing noise. Its wires are all twisted pairs, with input signals and output signals separately shielded, providing minimal cross talk between signals and offering the best protection against EMI/EMC problems.
1.2 Applications ❏ Event counting ❏ One shot output ❏ Programmable frequency output ❏ Frequency measurement ❏ Pulse width measurement ❏ PWM output ❏ Periodic interrupt generation ❏ Time-delay generation 1.
Install Driver from CD-ROM, then power-off PC Install Hardware and power-on PC Use driver utility to configure hardware Use test utility to test hardware Read examples & driver manual Start to write your own application Fig.
1.4 Software Overview Advantech offers a rich set of DLL drivers, third-party driver support and application software to help fully utilize the functions of your PCI-1780 card: Device Drivers (on the companion CD-ROM) ❏ LabVIEW driver* ❏ Advantech ActiveDAQ ❏ Advantech GeniDAQ ❏ Programming choices for DA&C cards: You may use Advantech application software such as Advantech Device Drivers.
1.5 Device Drivers Programming Roadmap This section will provide you a roadmap to demonstrate how to build an application from scratch using Advantech Device Drivers with your favorite development tools such as Visual C++, Visual Basic, Delphi and C++ Builder. The step-by-step instructions on how to build your own applications using each development tool will be given in the Device Drivers Manual. Moreover, a rich set of example source code is also given for your reference.
For information about using other function groups or other development tools, please refer to the Creating Windows 95/NT/2000 Application with Device Drivers chapter and the Function Overview chapter on the Device Drivers Manual. Programming with Device Drivers Function Library Advantech Device Drivers offers a rich function library to be utilized in various application programs.
1.6 Accessories Advantech offers a complete set of accessory products to support the PCI-1780 card. These accessories include: Wiring Cable ❏ PCL-10168 The PCL-10168 shielded cable is specially designed for PCI-1780 cards to provide high resistance to noise. To achieve better signal quality, the signal wires are twisted in such a way as to form a “twisted-pair cable,” reducing cross-talk and noise from other signal sources.
2. Installation This chapter gives users a package item checklist, proper instructions about unpacking and step-by-step procedures for both driver and card installation. 2.1 Unpacking After receiving your PCI-1780 package, please inspect its contents first. The package should contain the following items: ; PCI-1780 card ; Companion CD-ROM (DLL driver included) ; User’s Manual The PCI-1780 card harbors certain electronic components vulnerable to electrostatic discharge (ESD).
Also, pay extra caution to the following aspects to ensure proper installation: a Avoid physical contact with materials that could hold static electricity such as plastic, vinyl and Styrofoam. a Whenever you handle the card, grasp it only by its edges. DO NOT TOUCH the exposed metal pins of the connector or the electronic components. Note: ✎ Keep the anti-static bag for future use. You might need the original bag to store the card if you have to remove the card from the PC or transport it elsewhere.
2.2 Driver Installation We recommend you to install the driver before you install the PCI-1780 card into your system, since this will guarantee a smooth installation process. The Advantech Device Drivers Setup program for the PCI-1780 card is included on the companion CD-ROM that is shipped with your DA&C card package. Please follow the steps below to install the driver software: Step 1: Insert the companion CD-ROM into your CD-ROM drive.
Step 3: Select the Individual Drivers option. Step 4: Select the specific device then just follow the installation instructions step by step to complete your device driver setup. Fig. 2-2 Different options for Driver Setup For further information on driver-related issues, an online version of Device Drivers Manual is available by accessing the following path: Start/Programs/Advantech Device Drivers V2.0a/Device Driver Manual 2.
Step 1: Turn off your computer and unplug the power cord and cables. TURN OFF your computer before installing or removing any components on the computer. Step 2: Remove the cover of your computer. Step 3: Remove the slot cover on the back panel of your computer. Step 4: Touch the metal part on the surface of your computer to neutralize the static electricity that might be on your body. Step 5: Insert the PCI-1780 card into a PCI slot. Hold the card only by its edges and carefully align it with the slot.
Fig. 2-3 The device name listed in the Device Manager Note: ✎ If your card is properly installed, you should see the device name of your card listed on the Device Manager tab. If you do see your device name listed on it but marked with an exclamation sign “!”, it means your card has not been correctly installed. In this case, remove the card device from the Device Manager by selecting its device name and press the Remove button. Then go through the driver installation process again.
2.4 Device Setup & Configuration The PCI-1780 Utility program is a utility that allows you to setup, configure and test your device, and later store your settings on the system registry. These settings will be used when you call the APIs of Advantech Device Drivers. Setting Up the Device Step 1: To install the I/O device for your card, you must first run the Device Manager program (by accessing Start/Programs/ Advantech Device Drivers V2.0).
Step 3: Scroll down the Supported Devices box to find the device that you wish to install, then click the Add… button to evoke the Existing unconfigured PCI-1780 dialog box such as one shown in Fig. 2-5. The Existing unconfigured PCI-1780 dialog box lists all the installed devices on your system. Select the device you want to configure from the list box and press the OK button. Fig.
Step 4: After you have finished configuring the device, click OK and the device name will appear in the Installed Devices box as seen below: Fig. 2-6 The Device Name appearing on the list of devices box Note: ✎ As we have noted, the device name “001:” begins with a device number “000”, which is specifically assigned to each card. The device number is passed to the driver to specify which device you wish to control.
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3. Signal Connections 3.1 Overview Maintaining signal connections is one of the most important factors in ensuring that your application system is sending and receiving data correctly. A good signal connection can avoid unnecessary and costly damage to your PC and other hardware devices. This chapter provides useful information about how to connect input and output signals to the PCI-1780 via the I/O connector. 3.
Board ID setting (SW1) ID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 ID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 ID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 ID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Note: On: 1, Off: 0 20 Board ID 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
3.3 Signal Connections Pin Assignment Figure 3-2 shows the pin assignments for the 68-pin I/O connector on the PCI-1780.
I/O Connector Signal Description Table 3-2 I/O connector signal descriptions Signal Name Reference Direction Description GND - - +5V GND Output +5 VDC source FOUT<0..3> GND Output Frequency output channels OUT<0..7> GND Output Counter output channels DO<0..7> GND Output Digital output channels EXT_CLK GND Input External clock input CLK<0..7> GND Input Clock input channels GATE<0..7> GND Input Gate control channels DI<0..
Period measurement This approach is a particular fit for a low frequency signal. Counter 0 Unknown Signal GATE OUT CLK Counter 1 GATE OUT CLK Standard Clock Figure 3-3: Period measurement Implementing this measurement needs two counters. One for the up cycle period and another for the down cycle period. These added together gives the total period. The duty cycle can also be calculated by the up period being divided by the total period. Connect the unknown signal to each counter's Gate.
Frequency measurement This approach is a particular fit for a high frequency signal. Counter 0 GATE Counter 1 GATE OUT OUT CLK CLK Standard Clock Unknown Signal Figure 3-4: Frequency measurement Implementing this measurement needs two counters. One for the up cycle period, another for the down cycle period. Adding them together gives the total period. The duty cycle can also be calculated by dividing the up period by the total period. Connect the unknown signal to each counter's Gate.
Appendix A. Specifications Programmable Counter Channels Resolution Programmable Clock Source Programmable Counter Modes Max. Frequency Interrupt source 8 (independent) 16-bit 8 independent 12 20 MHz 8 counter outputs Digital Input/Output Input Channels Input Voltage 8 Low High Interrupt source Output Channels Output Voltage General I/O Connector Type Dimensions Low High 0.8 V max. 2.4 V min. Channel 0 8 0.5 V max. @ 24 mA (sink) 2.4 V min.
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Appendix B.
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Appendix C. Register Structure and Format C.1 Overview The PCI-1780 is delivered with an easy-to-use 32-bit DLL driver for user programming under the Windows 2000/95/98/NT/ME/XP operating system. We advise users to program the PCI-1780 using the 32-bit DLL driver provided by Advantech to avoid the complexity of low-level programming by register. The most important consideration in programming the PCI-1780 at register level is to understand the function of the card's registers.
Table C-1 PCI-1780 register format (Part 1) Base Address + HEX W 00H PCI-1780 Register Format 15 14 13 12 11 10 9 8 02H CM9 CM8 04H CL15 CL14 CL13 CL12 CL11 CL10 CL9 CL8 CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8 CM6 CM5 CM4 CM3 CM2 CM1 CM0 CL6 CL5 CL4 CL3 CL2 CL1 CL0 CH6 CH5 CH4 CH3 CH2 CH1 CH0 C2 C1 C0 CL7 CH7 Counter 1 Mode CM15 CM14 CM13 CM12 CM11 CM10 CM9 CM8 CM7 CM6 CM5 CM4 CM3 CM2 CM1 CM0 CL6 CL5 CL4 CL3 CL2 CL1 CL0 CH6 CH5 CH4 CH3 CH
Table C-1 PCI-1780 register format (Part 2) Base Address + HEX W 10H PCI-1780 Register Format 15 14 13 12 11 10 9 8 12H CM9 CM8 14H CL15 CL14 CL13 CL12 CL11 CL10 CL9 CL8 CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8 CM6 CM5 CM4 CM3 CM2 CM1 CM0 CL6 CL5 CL4 CL3 CL2 CL1 CL0 CH6 CH5 CH4 CH3 CH2 CH1 CH0 C2 C1 C0 CL7 CH7 Counter 3 Mode CM15 CM14 CM13 CM12 CM11 CM10 CM9 CM8 CM7 CM6 CM5 CM4 CM3 CM2 CM1 CM0 CL6 CL5 CL4 CL3 CL2 CL1 CL0 CH6 CH5 CH4 CH3 CH
Table C-1 PCI-1780 register format (Part 3) Base Address + HEX W 20H PCI-1780 Register Format 15 14 13 12 11 10 9 22H CM9 CM8 24H CL15 CL14 CL13 CL12 CL11 CL10 CL9 CL8 CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8 CM6 CM5 CM4 CM3 CM2 CM1 CM0 CL6 CL5 CL4 CL3 CL2 CL1 CL0 CH6 CH5 CH4 CH3 CH2 CH1 CH0 C2 C1 C0 CL7 CH7 Counter 5 Mode CM15 CM14 CM13 CM12 CM11 CM10 CM9 CM8 CM7 CM6 CM5 CM4 CM3 CM2 CM1 CM0 CL6 CL5 CL4 CL3 CL2 CL1 CL0 CH6 CH5 CH4 CH3 CH2
Table C-1 PCI-1780 register format (Part 4) Base Address + HEX W 30H PCI-1780 Register Format 15 14 13 12 11 10 9 8 32H CM9 CM8 34H CL15 CL14 CL13 CL12 CL11 CL10 CL9 CL8 CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8 CM6 CM5 CM4 CM3 CM2 CM1 CM0 CL6 CL5 CL4 CL3 CL2 CL1 CL0 CH6 CH5 CH4 CH3 CH2 CH1 CH0 C2 C1 C0 CL7 CH7 Counter 7 Mode CM15 CM14 CM13 CM12 CM11 CM10 CM9 CM8 CM7 CM6 CM5 CM4 CM3 CM2 CM1 CM0 CL6 CL5 CL4 CL3 CL2 CL1 CL0 CH6 CH5 CH4 CH3 CH
Table C-1 PCI-1780 register format (Part 5) Base Address + HEX W PCI-1780 Register Format 15 14 13 12 11 10 9 8 CE7 R W 44H 48H R DIO R 3 2 1 0 CE5 CE4 CE3 CE2 CE1 CE0 C6 C5 C4 C3 C2 C1 C0 C6 C5 C4 C3 C2 C1 C0 CE6 C7 Interrupt Status Clear Interrupt DI0 C7 N/A Digital Output DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Digital Input DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 BD3 BD2 BD1 BD0 N/A W 4EH 4 Interrupt Control R W 5 N/A R 42H 6 Command Enable 40H W
Table C-1 PCI-1780 register format (Part 6) Base Address + HEX W 50H PCI-1780 Register Format 15 14 13 12 11 10 9 FS2 FS1 8 52H FS0 54H 56H FOE FS2 FS1 FS0 58H 5AH FOE FS2 FS1 FS0 5CH 5EH 0 DV3 DV2 DV1 DV0 DV3 DV2 DV1 DV0 DV3 DV2 DV1 DV0 DV3 DV2 DV1 DV0 DV3 DV2 DV1 DV0 DV3 DV2 DV1 DV0 DV3 DV2 DV1 DV0 DV3 DV2 DV1 DV0 FOUT 3 Control FOE FS2 FS1 FS0 N/A FOUT 4 Control FOE FS2 FS1 FS0 N/A FOUT 5 Control FOE FS2 FS1 FS0 N/A FOUT 6 Control FO
C.3 Counter 0/1/2/3/4/5/6/7 mode — BASE+00/08/10/18/20/28/30/38H Table C-2 PCI-1780 Register for counter 0/1/2/3/4/5/6/7 mode Base Addr.
CM5 Count control (reload) 0 Reload from LOAD register 1 Reload from LOAD or HOLD register CM6 Count control (special gate) 0 Disable special gate 1 Enable special gate CM7 Count control (special gate) 0 Count on rising edge 1 Count on falling edge CM11 ~ CM8 Count source selection 0000 Internal clock 0001 OUT N-1 0010 CLK N 0011 CLK N-1 0100 FOUT 0 0101 FOUT 1 0110 FOUT 2 0111 FOUT 3 1000 FOUT 4 1001 FOUT 5 1010 FOUT 6 1011 FOUT 7 1100 GATE N-1 1101 N/A 1110 N/A 1111 N/A CM13 ~ CM12 Gate source se
CM14 Gating polarity selection 0 High level for level active, rising edge for edge active 1 CM15 Low level for level active, falling edge for edge active Gate active edge or level 0 Level active 1 Edge active 38
C.4 Counter 0/1/2/3/4/5/6/7 load — BASE+02/0A/12/1A/22/2A/32/3AH Table C-3 PCI-1780 Register for counter 0/1/2/3/4/5/6/7 load Base Addr.
C.5 Counter 0/1/2/3/4/5/6/7 hold — BASE+04/0C/14/1C/24/2C/34/3CH Table C-4 PCI-1780 Register for counter 0/1/2/3/4/5/6/7 hold Base Addr.
C.6 Counter 0/1/2/3/4/5/6/7 command — BASE+06/0E/16/1E/26/2E/36/3EH Table C-5 PCI-1780 Register for counter 0/1/2/3/4/5/6/7 command Base Addr.
C.7 Command enable — BASE+40H Table C-6 PCI-1780 Register for command enable Base Addr.
C.8 Interrupt control — BASE+42H Table C-7 PCI-1780 Register for interrupt control Base Addr. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C6 C5 C4 C3 C2 C1 C0 Interrupt control 42H W DI0 C7 Cn Counter interrupt enable bit (n: 0 ~ 7) 0 Disable interrupt for this counter 1 Enable interrupt for this counter DI0 Interrupt enable bit 0 Disable interrupt for DI0 1 Enable interrupt for DI0 C.9 Interrupt status — BASE+42H Table C-8 PCI-1780 Register for interrupt status Base Addr.
C.10 Clear interrupt — BASE+44H Write any data to these two bytes to clear the interrupt. Table C-9 PCI-1780 Register for clear interrupt Base Addr. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 2 1 0 Clear interrupt 44H W C.11 Digital output — BASE+48H Table C-10 PCI-1780 Register for digital output Base Addr. 15 14 13 12 11 10 9 8 7 6 5 4 Digital output 48H W DO7 DO6 DO5 DO4 DO3 DO2 DO1 C.
C.13 Board ID — BASE+4EH The PCI-1780 offers Board ID register BASE+4EH. With correct Board ID settings, users can easily identify and access each card during hardware configuration and software programming. Table C-12 PCI-1780 Register for board ID Base Addr.
C.14 FOUT 0/1/2/3/4/5/6/7 control — BASE + 50~5FH Table C-13 PCI-1780 Register for FOUT 0/1/2/3/4/5/6/7 Control Base Addr.
FS2 ~ FS0 FOUT source 000 External clock 001 CLK N 010 FOUT N-1 011 10 MHz clock 100 1 MHz clock 101 100 KHz clock 110 10 KHz clock 111 1 KHz clock FOE FOUT output enable 0 Disable 1 Enable 47
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Appendix D. Waveform of each mode The PCI-1780 offers 16 powerful counter functions to fulfill your industrial or laboratory applications. This chapter will describe each mode in detail with the waveform diagram. Counter mode descriptions Counter Mode register bits CM15-CM12 and CM6-CM4 select the operating mode for each counter (see Table D-1). To simplify references to a particular mode, each mode is assigned a letter from A through X.
As is fully explained in the TC section of the document, for these modes the counter is actually stopped or disarmed following the active-going source edge which drives the counter out of TC. In other words, since a counter in the TC state always counts, irrespective of it's gating of arming status, the stopping or disarming of the count sequence is delayed until TC is terminated.
D.1 Mode A waveform Software-Triggered Strobe with No Hardware Gating Mode A is one of the simplest operating modes. The counter will be available for countering source edges when it is issued and ARM command. On each TC the counter will reload from the Load register and automatically disarm itself, inhibiting further counting. Counting will resume when a new ARM command is issued.
D.2 Mode B waveform Software-Triggered Strobe with Level Gating Mode B is identical to Mode A except that source edges are counted only when the assigned Gate is active. The counter must be armed before counting can occur. Once armed, the counter will count all source edges that occur while the Gate is active and disregard those edges which occur while the Gate is inactive. This permits the Gate to turn the count process on and off.
D.3 Mode C waveform Hardware-Triggered Strobe Mode C is identical to Mode A, except that counting will not begin until a Gate edge is applied to the armed counter, the counter must be armed before application of the triggering Gate edge; Gate edges applied to a disarmed counter are disregarded. The counter will start counting on the first source edge after the triggering Gate edge and will continue counting until TC. At TC, the counter will reload from the Load register and automatically disarm itself.
D.4 Mode D waveform Rate Generator with No Hardware Gating Mode D is typically used in frequency generation applications. In this mode, the Gate input does not affect counter operation. Once armed, the counter will count to TC repetitively. On each TC the counter will reload itself from the Load register; hence the Load register value determines the time between TCs. A square wave rate generator may be obtained by specifying the TC Toggled output mode in the Counter Mode register.
D.5 Mode E waveform Rate Generator with Level Gating Mode E is identical to Mode D, except the counter will only count those source edges that occur while the Gate input is active. This feature allows the counting process to be enabled and disabled under hardware control. A square wave rate generator may be obtained by specifying the TC Toggled output mode.
D.6 Mode F waveform Non-Retriggerable One-Shot Mode F provides a non-retriggerable one-shot timing function. The counter must be armed before it will function. Application of a Gate edge to the armed counter will enable counting. When the counter reaches TC, it will reload itself from the Load register. The counter will then stop counting, awaiting a new Gate edge. Note that unlike Mode C, a new ARM command is not needed after TC, only a new Gate edge.
D.7 Mode G waveform Software-Triggered Delayed Pulse One-Shot In Mode G, the Gate does not affect the counter's operation. Once armed, the counter will count to TC twice and then automatically disarm itself. For most applications, the counter will initially be loaded from the Load register either by a LOAD command or by the last TC of an earlier timing cycle. Upon counting to the first TC, the counter will reload itself from the Hold register.
D.8 Mode H waveform Software-Triggered Delayed Pulse One-Shot with Hardware Gating Mode H is identical to Mode G except that the Gate input is used to qualify which source edges are to be counted. The counter must be armed for counting to occur. Once armed, the counter will count all source edges that occur while the Gate is active and disregard those source edges that occur while the Gate is inactive. This permits the Gate to turn the count process on and off.
D.9 Mode I waveform Hardware-Triggered Delayed Pulse Strobe Mode I is identical to Mode G, except the counting will not begin until a Gate edge is applied to an armed counter. The counter must be armed before application of the triggering Gate edge; Gate edges applied to a disarmed counter are disregarded. An armed counter will start counting on the first source edge after the triggering Gate edge. Countering will then proceed in the same manner as in Mode G.
D.10 Mode J waveform Variable Duty Cycle Rate Generator with No Hardware Gating Mode J will find the greatest usage in frequency generation applications with variable duty cycle requirements. Once armed, the counter will count continuously until it is issued a DISARM command. On the first TC, the counter will be reloaded from the Hold register. Counting will then proceed until the second TC at which time the counter will be reloaded from the Load register.
D.11 Mode K waveform Variable Duty Cycle Rate Generator with Level Gating Mode K is identical to Mode J except that source edges are only counted when the Gate is active. The counter must be armed for counting to occur. Once armed, the counter will count all source edges that occur while the Gate is active and disregard those source edges that occur while the Gate is inactive. This permits the Gate to turn the count process on and off.
D.12 Mode L waveform Hardware-Triggered Delayed Pulse One-Shot Mode L is similar to Mode J except that counting will not begin until a Gate edge is applied to an armed counter. The counter must be armed before application of the triggering Gate edge; Gate edges applied to a disarmed counter are disregarded. The counter will start counting source edges and counting will proceed until the second TC.
D.13 Mode O waveform Hardware-Triggered Strobe with Edge Disarm Mode O, shown in Figure O, is identical to Mode C except that the counter will be disarmed while an inactive-going Gate edge is applied to the counter. And the counter will hold the count value until it is issued a LOAD command or REST command.
D.14 Mode R waveform Non-Retriggerbale One-Shot with Edge Disarm Mode R is identical to Mode F except that the counter will be disarmed while an inactive-going Gate edge is applied to the counter. And the counter will hold the count value until it is issued a LOAD command or REST command.
D.15 Mode U waveform Hardware-Triggered Delayed Pulse Strobe with Edge Disarm Mode U is identical to Mode I except that the counter will be disarmed while the Gate an inactive-going Gate edge is applied to the counter. And the counter will hold the count value until it is issued a LOAD command or REST command.
D.16 Mode X waveform Hardware-Triggered Delayed Pulse One-Shot with Edge Disarm Mode X is identical to Mode L except that the counter will be disarmed while an inactive-going Gate edge is applied to the counter. And the counter will hold the count value until it is issued a LOAD command or REST command.
