User manual

15 PCI-1750 User Manual
Chapter 3 Operation
3.3 Timer and Counter
3.3.1 Introduction
The PCL-1750 includes one 8254 compatible programmable timer/counter chip
which provides two 16-bit timers and one counter, designated as Timer 0, Timer 1
and Counter 2. Timer 0 and Timer 1 are cascaded to be a 32-bit timer, with its input
connected to a 10 MHz oscillator and its gate control pulled high (enabled). Counter 2
of the 8254 chip is a 16-bit high-speed (1 MHz) isolated event counter (it shares a pin
with isolated IDI 15). The block diagram of the timer/counter system of PCI-1750 is
shown in Figure 3.3. Timers 0 and 1 are usually set in mode 3 (square wave genera-
tor) to generate periodic watchdog interrupts. Counter 2 can be set in mode 0 (stop
on terminal count) for measuring frequency, or in mode 3 (square wave generator) to
generate periodic watchdog interrupts or to be used as an event counter. For more
details on the operating modes of the 8254 counter chip, please refer to Appendix A.
Figure 3.3 Block diagram of timer/counter
3.3.2 Timer/Counter Frequency and Interrupt
The input clock frequency of the counter/timers is 10 MHz. The output of both Timer 1
and Counter 2 can generate interrupts to the system (refer to Section 3.3). The maxi-
mum and minimum timer interrupt frequency is (10 MHz)/(2x2)=(2.5 MHz) and (10
MHz)/(65535*65535)=0.002328 Hz, respectively.
The gates of the counter/timers are internally pulled to +5 V, keeping the gate control
always enabled.