User manual

PCI-1750 User Manual 20
A.1 The Intel 8254
The PCI-1750 uses one Intel 8254 compatible programmable interval timer/counter
chip. The popular 8254 offers three independent 16-bit down counters. Each counter
has a clock input, control gate and an output. You can program each counter for max-
imum count values from 2 to 65535.
The 8254 has a maximum input clock frequency of 10 MHz. The PCI-1750 provides
10 MHz input frequencies to the counter chip from an on-board crystal oscillator.
On the PCI-1750, the 8254 chip's Timer 0 and Timer 1 are cascaded to be a 32-bit
programmable timer.
A.1.1 Counter read/write and control registers
The 8254 programmable interval timer uses four registers at addresses BASE +
24(Dec), BASE + 25(Dec), BASE + 26(Dec) and BASE + 27(Dec) for read, write and
control of counter functions.
Register functions appear below:
Since the 8254 counter uses a 16-bit structure, each section of read/write data is split
into a least significant byte (LSB) and most significant byte (MSB). To avoid errors it
is important that you make read/write operations in pairs and keep track of the byte
order.
The data format for the control register appears below:
A.1.1.1 Description
SC1 & SC0 Select counter
RW1 & RW0 Select Read/Write Operation
Register Function
BASE + 24(Dec) Counter 0 read/write
BASE + 25(Dec) Counter 1 read/write
BASE + 26(Dec) Counter 2 read/write
BASE + 27(Dec) Counter control word
BASE+27(Dec) 8254 control, standard mode
Bit D7D6D5D4D3D2D1D0
Value SC1 SC0 RW1 RW0 M2 M1 M0 BCD
Counter SC1 SC0
000
101
210
Read-back command 1 1
Operation RW1 RW0
Counter Latch 0 0
Read/Write LSB 0 1
Read/Write MSB 1 0
Read/Write LSB first then MSB 1 1