User manual

PCI-1761 User Manual 28
C.6 I n t e r r u p t Sta t u s R eg is t e r - B A SE + 3 H / 4 H /5 H
The Interrupt Status Register control the status of eight interrupt signal sources
(IDI0 ~ IDI7).
IDInF Interrupt flag bits (n = 0 ~ 7)
This bit is a flag indicating the status of an interrupt.
User can read this bit to get the status of the interrupt
0 No interrupt
1 Interrupt occurred
IDInRF Interrupt enable control bits (n = 0 ~ 7)
Read this bit to Enable/Disable the interrupt.
0 Disable
1 Enable
IDInEN Interrupt triggering control bits (n = 0 ~ 7)
The interrupt can be triggered by a rising edge or
falling edge of the interrupt signal, as determined by
the value in this bit.
0 Rising edge trigger
1 Falling edge trigger
Table C.5: Register for Interrupt Status
Read Interrupt Status Register
Bit # 76543210
BASE +3H IDI7EN IDI6EN IDI5EN IDI4EN IDI3EN IDI2EN IDI1EN IDI0EN
BASE +4H IDI7RF IDI6RF IDI5RF IDI4RF IDI3RF IDI2RF IDI1RF IDI0RF
BASE +5H IDI7F IDI6F IDI5F IDI4F IDI3F IDI2F IDI1F IDI0F