Specifications

5
Data Type Structure Section 1-4
1.3.1 Parameter Maximum Waiting Time for Response
This timer indicates the length of time that the operating terminal (master) waits for
the response from the PLC (slave).
Permitted values are in the range of 0 ms to 65535 ms.
The default value is 500 ms.
This value must be increased when using a CPU with two PU interfaces (see „Guid-
ance for the employment of CPUs with 2 PU interfaces”).
1.3.2 Parameter Delay Until Connection Setup
Specifies the period of time that the terminal allows to elapse after an unsuccessful
attempt to establish the connection and before making another attempt.
Permitted values are in the range of 5000 ms to 255000 ms.
The default value is 10000 ms.
1.3.3 Parameter Fast Data Block Access
The base address for each data block being used is determined only once and this
information is stored temporarily in a local buffer with 10 positions. Any subsequent
accesses continue to operate with the information stored in the local buffer. The
information in the buffer is erased upon restarting the terminal or upon a resynchro-
nization after a communication error.
Important:
In this case, do not modify the size of data blocks or compress the PLC memory
while the connection between the terminal and the PLC is still being established!
If a terminal and a programming unit are simultaneously connected to the PLC by
means of a multiplexer, then any value of the data block that is altered via the
programming unit and transferred into the PLC, also results in a change of the
address location of the data block. In this case, the cache should be deactivated.
1.4 Data Type Structure
a) Alphanumerical Texts
Are stored in the memory byte for byte in ascending address order.
b) Counter
A distinction is made between variables which have been assigned a counter ad-
dress and variables which have been assigned another PLC address.
Counter address
When accessing counter addresses, the count value is interpreted in the binary
format and the control bits of the counter are masked out. Therefore, to avoid con-
trol bits from being erased, counter addresses should be accessed in the read-
mode only.