User manual

10 GR-LEON4-ITX Development Board
User Manual
2 ELECTRICAL DESIGN
2.1 LEON4 ASIC
The Aeroflex Gaisler LEON4 processor core is a synthesizable VHDL model of a 32-bit
processor compliant with the SPARC V8 architecture. The core is highly configurable and
particularly suitable for high performance multi-core system-on-a-chip (SOC) designs.
The core is interfaced using the AMBA 2.0 AHB bus and supports the IP core plug&play
method provided in the Aeroflex Gaisler IP library (GRLIB). The processor can be efficiently
implemented on FPGA and ASIC technologies and uses standard synchronous memory
cells for caches and register file. The processor supports the MUL, MAC and DIV
instructions and an optional IEEE-754 floating-point unit (FPU) and Memory Management
Unit (MMU). The LEON4 cache system consists of separate I/D multi-set Level-1 (L1)
caches with up to 4 ways per cache, and an optional Level-2 (L2) cache for increased
performance in data intensive applications. The LEON4 pipeline uses 64-bit internal
load/store data paths, with an AMBA AHB interface of either 64- or 128-bit. Branch
prediction, 1-cycle load latency and a 32x32 multiplier results in a performance of 1.7
DMIPS/MHz, or 2.1 Coremark/MHz.
The wider interfaces provides higher bus and memory bandwidth which is necessary when
designing ASICs with high clock frequencies (800 MHz and above). The LEON4 is fully
software compatible with previous LEON processors. The configurability of LEON4 allows
designers to optimize the processor for performance, power consumption, I/O throughput,
silicon area and cost.
As a technology demonstrator, Aeroflex Gaisler has implemented a representative LEON4
configuration in a Structured ASIC from eASIC technologies.
This design consists of dual core LEON4 processors and a set of IP cores connected
through AMBA AHB/APB buses as represented in Figure 2-2.
© Aeroflex Gaisler AB August 2010, Rev. 0.3
Figure 2-1: LEON4 Core Block Diagram