Specifications

Status and Events
3-8 AFG3000 Series Arbitrary/Function Generators Programmer Manual
Questionable Event Register (QEVR). This register has the same content as the
Questionable Condition Register.
Questionable Condition Register (QCR). The Questionable Condition Register is
made up of sixteen bits which note the occurrence of two types of events.
Figure 3-5: Questionable Condition Register (QCR)
Enable Registers
There are four types of enable registers:
 Event Status Enable Register (ESER), page 3-8
 Service Request Enable Register (SRER), page 3-9
 Operation Enable Register (OENR), page 3-9
 Questionable Enable Register (QENR), page 3-10
Each bit in the enable registers corresponds to a bit in the controlling status register.
By setting and resetting the bits in the enable register, you can determine whether
or not events that occur will be registered to the status register and queue.
Event Status Enable Register (ESER). The ESER consists of bits defined exactly the
same as bits 0 through 7 in the SESR register. You can use this register to control
whether or not the Event Status Bit (ESB) in the SBR should be set when an event
has occurred, and to determine if the corresponding SESR bit is set.
To set the ESB in the SBR (when the SESR bit has been set), set the ESER bit
corresponding to that event. To prevent the ESB from being set, reset the ESER bit
corresponding to that event.
Table 3-4: QCR bit functions
Bit Function
15 to 12 ––––– Not used
11 OVHP Overheat protection. Indicates whether the instrument internal temper-
ature is in questionable condition.
10 to 6 ––––– Not used
5 FREQ Frequency. Indicates whether frequency accuracy of the signal is of
questionable quality.
4 to 0 ––––– Not used
FREQ
FREQ
76543210
7 6 5 4 3 2 1 0
9 8
9 8
15
15
10
10
12
12
13
13
14
14
11
11
OVHP
OVHP