Specifications
212   
Glossary
of data values to be found on the data 
bus. In the trigger sequence, range 
terms are considered to be true when 
any value within the range occurs.
relative Denotes time period or 
count of states between the current 
state and the previous state. 
remote display A remote display is 
a display other than the one 
connected to the product hardware. 
Remote displays must be identified to 
the network through an address 
location.
remote session A remote session is 
when you run the logic analyzer using 
a display that is located away from 
the product hardware. 
right-click When using a mouse for 
a pointing device, to right-click an 
item, position the cursor over the 
item, and then quickly press and 
release the right mouse button.
sample A data sample is a portion of 
a data set, sometimes just one point. 
When an instrument samples the 
target system, it is taking a single 
measurement as part of its data 
acquisition cycle.
Sampling Use the selections under 
the logic analyzer Sampling tab to tell 
the logic analyzer how you want to 
make measurements, such as State 
vs. Timing.
secondary branch The secondary 
branch is indicated in the Trigger 
sequence step dialog box as the Else 
on selection. The destination of the 
secondary branch can be specified as 
any other active sequence state. See 
also primary branch.
session A session begins when you 
start a local session or remote 
session from the session manager, 
and ends when you select Exit from 
the main window. Exiting a session 
returns all tools to their initial 
configurations.
skew Skew is the difference in 
channel delays between 
measurement channels. Typically, 
skew between modules is caused by 
differences in designs of 
measurement channels, and 
differences in characteristics of the 
electronic components within those 
channels. You should adjust 
measurement modules to eliminate 
as much skew as possible so that it 
does not affect the accuracy of your 
measurements.
state measurement In a state 
measurement, the logic analyzer is 
clocked by a signal from the system 
under test. Each time the clock signal 










