Technical data

184 16800 Series Portable Logic Analyzers Service Guide
8 Theory of Operation
uninterrupted vector loop. The RAM output is sent to the
output driver circuit where the patterns are presented into a
logic configuration usable by the output pods.
Output Driver
The output driver circuit is made up of a series of FIFO queues,
latch/logic drivers, and multiplexers. The FIFO queue stabilizes
and pipelines the pattern flow between data memory and the
latch/logic drivers. The latch/logic drivers direct the pattern to
multiplexers at ECL voltage levels.
The multiplexers, one per channel, direct the programmed data
patterns to the output channels. The single- ended ECL- level
signals are converted to differential signals, which are routed to
the output cables and to the pods. Note that the differential ECL
output signal of the pattern generator modules not suited to
directly drive ECL circuitry.
Clock Circuit
The clock circuit paces the instruction memory, data memory,
and the FIFO pattern queue and multiplexers in the output
driver according to the desired data rate. Two phase-locked
loops drive the clock circuit according to the user- selected data
rate. The output of the multiplexer, which represents the
user- selected clocking rate, is distributed to the above listed
subcircuits on both the master board and all expander boards
that are configured with the master board.
The output of the clock select multiplexer is also distributed to
an external clock out circuit. The clock signal is routed to a
bank of external clock delay select multiplexer. The output of
this multiplexer, which represents the desired clock delay, is
directed to the external clock out pin on the clock pod.
Consequently either the internal clock or external clock is
redirected to the clock out pin with a user- selected clock delay.
CPU Interface
The CPU interface is a single programmable logic device (PLD)
which interprets the mainframe backplane logic and translates
the logic into signals to drive and program the pattern
generator module.