Technical data

Source Total Jitter Tests 4
U7232A DisplayPort Compliance Testing Notes 37
Table 3 Test Configuration Options
Configuration Option Description
Clock Recovery
Clock Recovery Order Set either a second order PLL or a first order PLL method is used to
recover the clock.
Clock Recovery Loop
Bandwidth
Sets the 3 dB bandwidth of the loop filter used by the PLL.
Clock Recovery Damping
Factor
Sets the damping factor which is the value that is used in designing
the second order PLL that is used to recover the clock. The damping
factor and the 3 dB bandwidth of the PLL are related to the natural
frequency using the following equation.
where:
Prerequisite Settings
Bandwidth Reduction Specifies the bandwidth frequency for the oscilloscope. This
configuration is only available when the Enhanced Bandwidth or Noise
Reduction option is installed on the oscilloscope.
Vswing Edge Sets the number of Edges used when performing the Vswing
measurement. The Vswing value is used to ensure that the waveform
is displayed as large as possible in the waveform viewing area.
Increasing this value increases the test run time but improves the
repeatability of the measurement.
VTop & VBase Edge Sets the number of edges required when making the VTop and VBase
measurements.
VH Pattern (Debug only) Sets the pattern that represents a high or one voltage when three or
more ones are transmitted in a row.
VL Pattern (Debug only) Sets the pattern that represents a low or zero voltage when three or
more zeros are transmitted in a row.
PRBS Validation Algorithm Settings
FFT Memory Length Sets the memory depth used for FFT calculations.
FFT Acquisition Sets the number of acquisitions used for FFT calculations.
Source Differential Tests
Eye Diagram
Eye Diagram Edge Sets the number of edges measured for the eye test.
ω
n
2πF
t
2ζ
2
1– 2ζ
2
1–()
2
1++
-------------------------------------------------------------------=
ω
n
the natural frequency of the PLL=
ζ the dampling factor of the PLL=
F
t
the 3 dB bandwidth of the PLL=