Agilent U7232A DisplayPort Electrical Performance Compliance Test Application Method of Implementation s Agilent Technologies
Notices © Agilent Technologies, Inc. 2007-2009 Manual Part Number No part of this manual may be reproduced in any form or by any means (including electronic storage and retrieval or translation into a foreign language) without prior agreement and written consent from Agilent Technologies, Inc. as governed by United States and international copyright laws. U7232-97004 Edition Fifth edition, March 2009 Printed in USA Agilent Technologies, Inc.
DisplayPort Automated Testing—At A Glance The Agilent U7232A DisplayPort Electrical Performance Compliance Test Application helps you verify DisplayPort Source device under test (DUT) compliance to DisplayPort specifications using an Agilent 8 GHz or greater Infiniium digital storage oscilloscope. The DisplayPort Electrical Performance Compliance Test Application: • Lets you select individual or multiple tests to run. • Lets you identify the device being tested and its configuration.
• Precision 3.5 mm BNC to SMA male adapter, Agilent p/n 54855- 67604, qty = 2 (provided with the Agilent Infiniium oscilloscope). • Calibration cable (provided with the Infiniium oscilloscopes). Use a good quality 50 Ω BNC cable for calibrating the oscilloscope. • E2655A/B probe de- skew fixture. • 1168A or 1169A probes and N5380A SMA probe head. • U7232A DisplayPort Electrical Performance Compliance Test Application license. • N5400A EZJIT Plus Jitter Analysis software license.
In This Book This manual describes the tests that are performed by the DisplayPort Electrical Performance Compliance Test Application in more detail; it contains information from (and refers to) the DisplayPort Specification Version 1.1, and it describes how the tests are performed. • Chapter 1, “Installing the DisplayPort Electrical Performance Compliance Test Application shows how to install and license the automated test application (if it was purchased separately).
Frequency and Modulation Deviation tests are normative tests whereas Deviation HF Variation tests are informative tests. • Chapter 14, “Source Rise- Fall Mismatch Single- Ended Tests (Informative) shows the probing and test procedure of the source rise and fall mismatch single- ended tests. • Chapter 15, “Source Intra Pair Skew Single- Ended Tests shows the probing and test procedure of the source intra pair skew single- ended tests.
See Also • The DisplayPort Electrical Performance Compliance Test Application’s online help, which describes: • Starting the tests. • Creating or opening a test project. • Setting up the DisplayPort test environment. • Setting up the source automated tests with W2642A DPTC. • Selecting tests. • Configuring selected tests. • Connecting the oscilloscope to the DUT. • Running the tests. • Viewing the test results. • Viewing/printing the HTML test report. • Saving test projects. • Understanding the HTML report.
U7232A DisplayPort Electrical Performance Compliance Test Application
Contents DisplayPort Automated Testing—At A Glance Required Equipment and Software 3 In This Book See Also 3 5 7 1 Installing the DisplayPort Electrical Performance Compliance Test Application Installing the Software 16 Installing the License Key 17 2 Preparing to Take Measurements W2641A DisplayPort Test Point Adapter Fixture Acquiring the Test Fixture 20 W2641A Test Fixture Description 20 Calibrating the Oscilloscope 20 21 Starting the DisplayPort Electrical Performance Compliance Test Applicati
5 Source Non-ISI Jitter Differential Tests Probing for Source Non-ISI Jitter Differential Tests Source Non-ISI Jitter Differential Tests Test Procedure 48 Test Condition 51 PASS Condition 52 Test References 52 46 48 6 Source Transition Time Differential Tests (Informative) Probing for Source Transition Time Differential Tests Source Transition Time Differential Tests Test Procedure 56 Test Condition 59 PASS Condition 59 Test References 60 54 56 7 Source Non Pre-Emphasis Level Differential Tests Probin
Source Pre-Emphasis Level Differential Tests Test Procedure 80 Test Condition 84 PASS Condition 85 Test References 85 80 10 Source Inter Pair Skew Differential Tests Probing for Source Inter Pair Skew Differential Tests Source Inter Pair Skew Differential Test Test Procedure 90 Test Condition 93 PASS Condition 93 Test References 94 88 90 11 Source Unit Interval Differential Tests (Informative) Probing for Source Unit Interval Differential Tests Source Unit Interval Differential Tests Test Procedure 98
Source Spread Spectrum Clocking (SSC) Differential Test 114 Spread Spectrum Modulation Frequency (Normative) 114 Spread Spectrum Modulation Deviation (Normative) 114 Deviation HF Variation (Informative) 114 Test Procedure 115 SSC Modulation Frequency Test Condition 118 SSC Modulation Deviation Test Condition 118 SSC Deviation HF Variation Test Condition 119 SSC Modulation Frequency PASS Condition 119 SSC Modulation Deviation PASS Condition 119 SSC Deviation HF Variation PASS Condition 119 Test References 12
Link Layer Protocol Tests 147 Link Layer Protocol - Pre-Emphasis 147 Link Layer Protocol - Level 147 Link Layer Protocol - Bit Rate 147 Test Procedure 148 Pre-Emphasis Test Condition 151 Level Test Condition 151 Bit Rate Test Condition 151 Pre-Emphasis PASS Condition 152 Level PASS Condition 152 Bit Rate PASS Condition 152 Test References 152 18 Sink Eye Diagram Tests Probing for Sink Eye Diagram Tests 154 Sink Eye Diagram Tests 156 Test Procedure 156 PASS Condition 161 Test References 162 19 Sink Total
Cable Eye Diagram Tests 186 Test Procedure 186 PASS Condition 191 Test References 192 22 Cable Total Jitter Tests Probing for Cable Total Jitter Tests 194 Cable Total Jitter Tests 196 Test Procedure 196 PASS Condition 201 Test References 201 23 Cable Non-ISI Jitter Tests Probing for Cable Non-ISI Jitter Tests Cable Non-ISI Jitter Tests Test Procedure 206 PASS Condition 211 Test References 212 204 206 24 Calibrating the Infiniium Oscilloscope and Probe Required Equipment for Calibration Internal Calib
U7232A DisplayPort Electrical Performance Compliance Test Application Method of Implementation 1 Installing the DisplayPort Electrical Performance Compliance Test Application Installing the Software 16 Installing the License Key 17 If you purchased the U7232A DisplayPort Electrical Performance Compliance Test Application version 2.01, you need to install the software and license key.
1 Installing the DisplayPort Electrical Performance Compliance Test Application Installing the Software 1 Make sure you have version 05.60 or higher of the Infiniium oscilloscope software or Version 1.31 or greater of baseline software by choosing Help>About Infiniium... from the main menu. 2 To obtain the DisplayPort Electrical Performance Compliance Test Application, go to Agilent website: http://www.agilent.com/find/scope- apps- sw.
Installing the DisplayPort Electrical Performance Compliance Test Application 1 Installing the License Key 1 Request a license code from Agilent by following the instructions on the Entitlement Certificate. You will need the oscilloscope’s “Option ID Number”, which you can find in the Help>About Infiniium... dialog box. 2 After you receive your license code from Agilent, choose Utilities>Install Option License....
1 18 Installing the DisplayPort Electrical Performance Compliance Test Application Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
U7232A DisplayPort Electrical Performance Compliance Test Application Method of Implementation 2 Preparing to Take Measurements W2641A DisplayPort Test Point Adapter Fixture 20 Calibrating the Oscilloscope 21 Starting the DisplayPort Electrical Performance Compliance Test Application 22 Online Help Topics 24 Before running the DisplayPort automated tests, you need to acquire the appropriate test fixtures, and you should calibrate the oscilloscope and probe.
2 Preparing to Take Measurements W2641A DisplayPort Test Point Adapter Fixture The W2641A test fixture is the Agilent DisplayPort test point adapter fixture that is used for all of the DisplayPort compliance tests. Acquiring the Test Fixture The W2641A DisplayPort test point adapter fixture can be acquired from Agilent Technologies. W2641A Test Fixture Description Figure 2 shows the top view of the W2641A test fixture.
Preparing to Take Measurements 2 Calibrating the Oscilloscope If you haven’t already calibrated the oscilloscope and probe, see Chapter 24, “Calibrating the Infiniium Oscilloscope and Probe. NOTE If the ambient temperature changes more than 5 degrees Celsius from the calibration temperature, internal calibration should be performed again. The delta between the calibration temperature and the present operating temperature is shown in the Utilities>Calibration menu.
2 Preparing to Take Measurements Starting the DisplayPort Electrical Performance Compliance Test Application 1 From the Infiniium oscilloscope’s main menu, choose Analyze>Automated Test Apps>DisplayPort Test.
2 Preparing to Take Measurements NOTE If DisplayPort Test does not appear in the Automated Test Apps menu, the DisplayPort Electrical Performance Compliance Test Application has not been installed (see Chapter 1, “Installing the DisplayPort Electrical Performance Compliance Test Application). Figure 3 shows the DisplayPort Electrical Performance Compliance Test Application main window.
2 Preparing to Take Measurements Online Help Topics For information on using the DisplayPort Electrical Performance Compliance Test Application, see the online help (which you can access by choosing Help>Contents... from the application’s main menu). The DisplayPort Electrical Performance Compliance Test Application’s online help describes: • Running the Compliance Test Application on a second monitor. • Starting the DisplayPort Electrical Performance Compliance Test Application.
U7232A DisplayPort Electrical Performance Compliance Test Application Method of Implementation 3 Source Eye Diagram Differential Tests Probing for Source Data Eye Diagram Differential Tests 26 Source Eye Diagram Differential Tests 28 This section provides the guidelines for source eye diagram differential tests using an Agilent 8 GHz or greater Infiniium oscilloscope, 1168A or 1169A probes, and the DisplayPort Electrical Performance Compliance Test Application.
3 Source Eye Diagram Differential Tests Probing for Source Data Eye Diagram Differential Tests When performing the data eye diagram test, the DisplayPort Electrical Performance Compliance Test Application will prompt you to make the proper connections. Your DisplayPort test environment setup on the Set Up tab must match the physical connection. Figure 4 and Figure 5 show a physical connection for making differential and single- ended connections. . Infiniium Oscilloscope N5380A SMA probe head.
Source Eye Diagram Differential Tests 3 . Infiniium Oscilloscope DUT SMA to SMP cables Data Channel Lane on the W2641A test fixture Figure 5 Differential Measurement Setup Using Two Single Ended Connections - Data Eye Diagram Tests (A Minus B Configuration) You can use any oscilloscope channel and connect it to any lane test point. You select the channels used for testing lanes in the Set Up tab of the DisplayPort Electrical Performance Compliance Test Application.
3 Source Eye Diagram Differential Tests Source Eye Diagram Differential Tests The eye diagram test provides a visual evaluation of the amplitude and timing variations of the waveform with the overall objective of obtaining a specified bit error rate in transmitted data. The test must use a PRBS 7 test pattern at all voltage levels. The test should be performed without pre- Emphasis.
Source Eye Diagram Differential Tests 3 6 In the DisplayPort Compliance Test Application, click the Set Up tab.
3 Source Eye Diagram Differential Tests Figure 7 Test Type Set Up for Data Eye Pattern Differential Tests 7 Set the Test Mode, Test Type, DUT Definition Settings, Fixture Type, Connection Type and Number of Channels according to the type of testing being done. Source tests are available in all the 3 test modes Compliance Conditions Only, User Defined Conditions and Targeted Characterization Testing.
Source Eye Diagram Differential Tests 3 Navigate to the Eye Diagram - Lane # - Eye Diagram Test where # is the lane number to be tested. Figure 8 Selecting Data Eye Pattern Differential Tests 8 Follow the DisplayPort Electrical Performance Compliance Test Application’s task flow to set up configuration options (see Table 1), run the test and view the test results. Options may vary depending on selected mode: Compliance Mode or Debug Mode.
3 Source Eye Diagram Differential Tests Table 1 Test Configuration Options Configuration Option Description Clock Recovery Settings Clock Recovery Order Set either a second order PLL or a first order PLL method to recover the clock. Clock Recovery Loop Bandwidth (D10.2) - 1.62 Gbps Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2 pattern is used. Please specify in correct format; xMHz, xkHz or xHz. Clock Recovery Loop Bandwidth (PRBS 7) 1.
Source Eye Diagram Differential Tests Table 1 3 Test Configuration Options Configuration Option Description Test Plan Check Mode Turn on test plan check mode to simulate the actual test plan run flow without actual tests being run. SSC Acquisitions Number of SSC cycle captured for SSC related tests. Maximum number is 25. Low Bit Rate SSC Smoothing Points Sets the number of smoothing points for SSC low pass filter when bit rate is 1.62 Gbps.
3 Source Eye Diagram Differential Tests PASS Condition The following table and figure define the mask for the eye measurements. There can be no signal trajectories entering into the mask. Table 2 shows the voltage and time coordinates for the mask used in the eye diagram. The specification states that either 400mV, 600mV, or 800mV setting must pass. Table 2 Eye Diagram Mask Coordinates Bit Rate Mask Point Reduced (1.62 Gb/s) High (2.7 Gb/s) 1 0.127, 0.000 0.210, 0.000 2 0.291, 0.160 0.355, 0.
Source Eye Diagram Differential Tests 3 Test References See Test 3.1: Eye Diagram Testing, in the DisplayPort- Compliance Test Specification Version 1.1.
3 36 Source Eye Diagram Differential Tests Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
U7232A DisplayPort Electrical Performance Compliance Test Application Method of Implementation 4 Source Total Jitter Differential Tests Probing for Source Total Jitter Differential Tests 38 Source Total Jitter Differential Tests 40 This section provides the guidelines for source total jitter differential tests using an Agilent 8 GHz or greater Infiniium oscilloscope, InfiniiMax probes, and the DisplayPort Electrical Performance Compliance Test Application.
4 Source Total Jitter Differential Tests Probing for Source Total Jitter Differential Tests When performing the source total jitter test, the DisplayPort Electrical Performance Compliance Test Application will prompt you to make the proper connections. Your DisplayPort test environment setup on the Set Up tab must match the physical connection. Figure 10 and Figure 11 show a physical connection for making differential and single- ended connections. . Infiniium Oscilloscope N5380A SMA probe head.
Source Total Jitter Differential Tests 4 . Infiniium Oscilloscope DUT SMA to SMP cables Data Channel Lane on the W2641A test fixture Figure 11 Differential Measurement Setup Using Two Single Ended Connections - Total Jitter Tests (A Minus B Configuration) You can use any oscilloscope channel and connect it to any lane test point. You select the channels used for testing lanes in the Set Up tab of the DisplayPort Electrical Performance Compliance Test Application.
4 Source Total Jitter Differential Tests Source Total Jitter Differential Tests To evaluate the total jitter accompanying the data transmission at either an explicit bit error rate of 10- 9 or through an approved estimation technique. This measurement is a data time interval error (Data- TIE) jitter measurement. (Reference: Table 3.13 VESA DisplayPort Standard). The overall system jitter budget allocates different amounts of jitter which each component of the system is allowed to contribute.
Source Total Jitter Differential Tests 4 Navigate to the Total Jitter - Lane # - where # is the lane number to be tested. Figure 12 Selecting Source Total Jitter Differential Tests 8 Follow the DisplayPort Electrical Performance Compliance Test Application’s task flow to set up configuration options (see Table 3), run the test and view the test results. Options may vary depending on selected mode: Compliance Mode or Debug Mode.
4 Source Total Jitter Differential Tests Table 3 Test Configuration Options Configuration Option Description Clock Recovery Settings Clock Recovery Order Set either a second order PLL or a first order PLL method to recover the clock. Clock Recovery Loop Bandwidth (D10.2) - 1.62 Gbps Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2 pattern is used. Please specify in correct format; xMHz, xkHz or xHz. Clock Recovery Loop Bandwidth (PRBS 7) 1.
Source Total Jitter Differential Tests Table 3 4 Test Configuration Options Configuration Option Description Test Plan Check Mode Turn on test plan check mode to simulate the actual test plan run flow without actual tests being run. SSC Acquisitions Number of SSC cycle captured for SSC related tests. Maximum number is 25. Low Bit Rate SSC Smoothing Points Sets the number of smoothing points for SSC low pass filter when bit rate is 1.62 Gbps.
4 Source Total Jitter Differential Tests PASS Condition Table 4 Total Jitter at Internal and Compliance Points. Transmitter package pin Transmitter Connector (TP2) High-bit Rate (2.7 Gb/s per lane) Ap-p 0.294 UI 0.420 UI Reduced-bit Rate (1.62 Gb/s per lane) Ap-p 0.180 UI 0.254 UI UI is Unit Interval. Test References See Test 3.12: Total Jitter (TJ) Measurements in the DisplayPort- Compliance Test Specification Version 1.1.
U7232A DisplayPort Electrical Performance Compliance Test Application Method of Implementation 5 Source Non-ISI Jitter Differential Tests Probing for Source Non-ISI Jitter Differential Tests 46 Source Non-ISI Jitter Differential Tests 48 This section provides the guidelines for source non- ISI jitter differential tests using an Agilent 8 GHz or greater Infiniium oscilloscope, InfiniiMax probes, and the DisplayPort Electrical Performance Compliance Test Application.
5 Source Non-ISI Jitter Differential Tests Probing for Source Non-ISI Jitter Differential Tests When performing the non- ISI jitter test, the DisplayPort Electrical Performance Compliance Test Application will prompt you to make the proper connections. Your DisplayPort test environment setup on the Set Up tab must match the physical connection. Figure 13 and Figure 14 show a physical connection for making differential and single- ended connections. . Infiniium Oscilloscope N5380A SMA probe head.
Source Non-ISI Jitter Differential Tests 5 . Infiniium Oscilloscope DUT SMA to SMP cables Data Channel Lane on the W2641A test fixture Figure 14 Differential Measurement Setup Using Two Single Ended Connections - Non-ISI Jitter Tests (A Minus B Configuration) You can use any oscilloscope channel and connect it to any lane test point. You select the channels used for testing lanes in the Set Up tab of the DisplayPort Electrical Performance Compliance Test Application.
5 Source Non-ISI Jitter Differential Tests Source Non-ISI Jitter Differential Tests To evaluate the Non- ISI jitter accompanying the data transmission at either an explicit bit error rate of 10- 9 or through an approved estimation technique. (Reference: Table 3.13 VESA DisplayPort Standard). The overall system jitter budget allocates different amounts of jitter which each component of the system is allowed to contribute. To exceed any of these limits is to violate the component level jitter budget.
Source Non-ISI Jitter Differential Tests 5 Navigate to the Non- ISI Jitter - Lane # - Non- ISI Jitter Test where # is the lane number to be tested. Figure 15 Selecting Source Non-Jitter Differential Tests 8 Follow the DisplayPort Electrical Performance Compliance Test Application’s task flow to set up configuration options (see Table 5), run the test and view the test results. Options may vary depending on selected mode: Compliance Mode or Debug Mode.
5 Source Non-ISI Jitter Differential Tests Table 5 Test Configuration Options Configuration Option Description Clock Recovery Settings Clock Recovery Order Set either a second order PLL or a first order PLL method to recover the clock. Clock Recovery Loop Bandwidth (D10.2) - 1.62 Gbps Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2 pattern is used. Please specify in correct format; xMHz, xkHz or xHz. Clock Recovery Loop Bandwidth (PRBS 7) 1.
Source Non-ISI Jitter Differential Tests Table 5 5 Test Configuration Options Configuration Option Description Test Plan Check Mode Turn on test plan check mode to simulate the actual test plan run flow without actual tests being run. SSC Acquisitions Number of SSC cycle captured for SSC related tests. Maximum number is 25. Low Bit Rate SSC Smoothing Points Sets the number of smoothing points for SSC low pass filter when bit rate is 1.62 Gbps.
5 Source Non-ISI Jitter Differential Tests PASS Condition Table 6 Non-ISI Jitter at Internal and Compliance Points. Transmitter package pin Transmitter Connector (TP2) High-bit Rate (2.7 Gb/s per lane) Ap-p 0.260 UI 0.276 UI Reduced-bit Rate (1.62 Gb/s per lane) Ap-p 0.160 UI 0.170 UI UI is Unit Interval. Test References See Test 3.12: Non- ISI Jitter (TJ) Measurements in the DisplayPort- Compliance Test Specification Version 1.1.
U7232A DisplayPort Electrical Performance Compliance Test Application Method of Implementation 6 Source Transition Time Differential Tests (Informative) Probing for Source Transition Time Differential Tests 54 Source Transition Time Differential Tests 56 This section provides the guidelines for source transition time differential tests using an Agilent 8 GHz or greater Infiniium oscilloscope, 1168A or 1169A probes, and the DisplayPort Electrical Performance Compliance Test Application.
6 Source Transition Time Differential Tests (Informative) Probing for Source Transition Time Differential Tests When performing the transition time test, the DisplayPort Electrical Performance Compliance Test Application will prompt you to make the proper connections. Your DisplayPort test environment setup on the Set Up tab must match the physical connection. Figure 16 and Figure 17 below show the differential and the single- ended connections for Transition Time Diffential Tests. .
Source Transition Time Differential Tests (Informative) 6 . Infiniium Oscilloscope DUT SMA to SMP cables Data Channel Lane on the W2641A test fixture Figure 17 Differential Measurement Setup Using Two Single Ended Connections Transition Time Tests (A Minus B Configuration) You can use any oscilloscope channel and connect it to any lane test point. You select the channels used for testing lanes in the Set Up tab of the DisplayPort Electrical Performance Compliance Test Application.
6 Source Transition Time Differential Tests (Informative) Source Transition Time Differential Tests Transition time testing measures the rise time and fall time across the outputs of a differential data lane. The transition is defined as the time interval between the normalized 20% and 80% amplitude levels. The transition time test should be performed at all bit rates supported without pre- Emphasis for 400 mV differential voltage swing. The source pattern should be a PRBS 7 waveform.
Source Transition Time Differential Tests (Informative) 6 Navigate to the Transition Time group, and check the rise time and fall time tests that you want to perform. Figure 18 Selecting Transition Time Differential Tests 9 Follow the DisplayPort Electrical Performance Compliance Test Application’s task flow to set up configuration options (see Table 7), make oscilloscope connections, run the tests, and view the tests results.
6 Source Transition Time Differential Tests (Informative) Table 7 Test Configuration Options Configuration Option Description Clock Recovery Settings Clock Recovery Order Set either a second order PLL or a first order PLL method to recover the clock. Clock Recovery Loop Bandwidth (D10.2) - 1.62 Gbps Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2 pattern is used. Please specify in correct format; xMHz, xkHz or xHz. Clock Recovery Loop Bandwidth (PRBS 7) 1.
Source Transition Time Differential Tests (Informative) Table 7 6 Test Configuration Options Configuration Option Description Test Plan Check Mode Turn on test plan check mode to simulate the actual test plan run flow without actual tests being run. SSC Acquisitions Number of SSC cycle captured for SSC related tests. Maximum number is 25. Low Bit Rate SSC Smoothing Points Sets the number of smoothing points for SSC low pass filter when bit rate is 1.62 Gbps.
6 Source Transition Time Differential Tests (Informative) Test References See section 3.6, in the DisplayPort- Compliance Test Specification Version 1.1.
U7232A DisplayPort Electrical Performance Compliance Test Application Method of Implementation 7 Source Non Pre-Emphasis Level Differential Tests Probing for Source Non Pre-Emphasis Level Differential Tests 62 Source Non Pre-Emphasis Level Test 64 This section provides the guidelines for source non pre- Emphasis level differential tests using an Agilent 8 GHz or greater Infiniium oscilloscope, 1168A or 1169A probes, and the DisplayPort Electrical Performance Compliance Test Application.
7 Source Non Pre-Emphasis Level Differential Tests Probing for Source Non Pre-Emphasis Level Differential Tests When performing the non pre- Emphasis level differential test, the DisplayPort Electrical Performance Compliance Test Application will prompt you to make the proper connections. Your DisplayPort test environment setup on the Set Up tab must match the physical connection.
Source Non Pre-Emphasis Level Differential Tests 7 . Infiniium Oscilloscope DUT SMA to SMP cables Data Channel Lane on the W2641A test fixture Figure 20 Differential Measurement Setup Using Two Single Ended Connections - Non Pre-Emphasis Level Tests (A Minus B Configuration) You can use any oscilloscope channel and connect it to any lane test point. You select the channels used for testing lanes in the Set Up tab of the DisplayPort Electrical Performance Compliance Test Application.
7 Source Non Pre-Emphasis Level Differential Tests Source Non Pre-Emphasis Level Test To evaluate the waveform peak differential amplitude to ensure signal is neither over, nor under driven. (Reference: Table 3.10 VESA DisplayPort Standard). The source is given a range of expected output for each level setting that correlates with the system budget elements such as cable loss and receiver eye minimum and max values. This test ensures that the system budget is obeyed.
Source Non Pre-Emphasis Level Differential Tests 7 . Figure 21 Selecting Non Pre-Emphasis Level Tests 9 Follow the DisplayPort Electrical Performance Compliance Test Application’s task flow to set up configuration options (see Table 8), make oscilloscope connections, run the tests, and view the test results. Options may vary depending on the selected mode: Compliance Mode or Debug Mode.
7 Source Non Pre-Emphasis Level Differential Tests Table 8 Test Configuration Options Configuration Option Description Clock Recovery Settings Clock Recovery Order Set either a second order PLL or a first order PLL method to recover the clock. Clock Recovery Loop Bandwidth (D10.2) - 1.62 Gbps Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2 pattern is used. Please specify in correct format; xMHz, xkHz or xHz. Clock Recovery Loop Bandwidth (PRBS 7) 1.
Source Non Pre-Emphasis Level Differential Tests Table 8 7 Test Configuration Options Configuration Option Description Test Plan Check Mode Turn on test plan check mode to simulate the actual test plan run flow without actual tests being run. SSC Acquisitions Number of SSC cycle captured for SSC related tests. Maximum number is 25. Low Bit Rate SSC Smoothing Points Sets the number of smoothing points for SSC low pass filter when bit rate is 1.62 Gbps.
7 Source Non Pre-Emphasis Level Differential Tests Table 9 Compared Levels Measurement VoltagePeak-Peak_LevelA VoltagePeak-Peak_LevelB 1 600mV nominal (0 dB) 400mV nominal (0 dB) 2 800mV nominal (0 dB) 600mV nominal (0 dB) 3* 1200mV nominal (0 dB)* 800mV nominal (0 dB). * if device optionally capable The resultants specifications are as identified below: Measurement 1: 0.8 dB ≤ Resultant ≤ 6.0 dB Measurement 2: 0.1 dB ≤ Resultant ≤ 5.1 dB Measurement 3: 0.8 dB ≤ Resultant ≤ 6.
U7232A DisplayPort Electrical Performance Compliance Test Application Method of Implementation 8 Source Overshoot Differential Tests (Informative) Probing for Source Overshoot Differential Tests 70 Source Overshoot Differential Tests 72 This section provides the guidelines for source overshoot differential tests using an Agilent 8 GHz or greater Infiniium oscilloscope, 1168A or 1169A probes, and the DisplayPort Electrical Performance Compliance Test Application.
8 Source Overshoot Differential Tests (Informative) Probing for Source Overshoot Differential Tests When performing the overshoot test, the DisplayPort Electrical Performance Compliance Test Application will prompt you to make the proper connections. Your DisplayPort test environment setup on the Set Up tab must match the physical connection. Figure 22 and Figure 23 below show the differential and the single- ended connections for Overshoot Differential Tests. .
Source Overshoot Differential Tests (Informative) 8 . Infiniium Oscilloscope DUT SMA to SMP cables Data Channel Lane on the W2641A test fixture Figure 23 Differential Measurement Setup Using Two Single Ended Connections Overshoot Tests (A Minus B Configuration) You can use any oscilloscope channel and connect it to any lane test point. You select the channels used for testing lanes in the Set Up tab of the DisplayPort Electrical Performance Compliance Test Application.
8 Source Overshoot Differential Tests (Informative) Source Overshoot Differential Tests Overshoot is a differential measurement across the outputs of a differential pair. The overshoot test should be performed at the lowest pixel rate. Test Procedure 1 Start the automated testing application as described in “Starting the DisplayPort Electrical Performance Compliance Test Application" on page 22. 2 Connect the W2641A test fixture or other appropriate fixture to the device under test (DUT).
8 Source Overshoot Differential Tests (Informative) Navigate to the Overshoot Test - Lane # - Overshoot Test where # is the lane number to be tested. Figure 24 Selecting Overshoot Differential Tests 9 Follow the DisplayPort Electrical Performance Compliance Test Application’s task flow to set up configuration options (see Table 10), make oscilloscope connections, run the tests, and view the tests results. Options may vary depending on the selected mode: Compliance Mode or Debug Mode.
8 Source Overshoot Differential Tests (Informative) Table 10 Test Configuration Options Configuration Option Description Clock Recovery Settings Clock Recovery Order Set either a second order PLL or a first order PLL method to recover the clock. Clock Recovery Loop Bandwidth (D10.2) - 1.62 Gbps Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2 pattern is used. Please specify in correct format; xMHz, xkHz or xHz. Clock Recovery Loop Bandwidth (PRBS 7) 1.
Source Overshoot Differential Tests (Informative) 8 Table 10 Test Configuration Options Configuration Option Description Test Plan Check Mode Turn on test plan check mode to simulate the actual test plan run flow without actual tests being run. SSC Acquisitions Number of SSC cycle captured for SSC related tests. Maximum number is 25. Low Bit Rate SSC Smoothing Points Sets the number of smoothing points for SSC low pass filter when bit rate is 1.62 Gbps.
8 76 Source Overshoot Differential Tests (Informative) Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
U7232A DisplayPort Electrical Performance Compliance Test Application Method of Implementation 9 Source Pre-Emphasis Level Differential Tests (Normative & Informative) Probing for Source Pre-Emphasis Level Differential Tests 78 Source Pre-Emphasis Level Differential Tests 80 This section provides the guidelines for source pre- Emphasis level differential tests using an Agilent 8 GHz or greater Infiniium oscilloscope, 1168A or 1169A probes, and the DisplayPort Electrical Performance Compliance Test Applica
9 Source Pre-Emphasis Level Differential Tests (Normative & Informative) Probing for Source Pre-Emphasis Level Differential Tests When performing the pre- Emphasis level differential test, the DisplayPort Electrical Performance Compliance Test Application will prompt you to make the proper connections. Your DisplayPort test environment setup on the Set Up tab must match the physical connection.
Source Pre-Emphasis Level Differential Tests (Normative & Informative) 9 . Infiniium Oscilloscope DUT SMA to SMP cables Data Channel Lane on the W2641A test fixture Figure 26 Differential Measurement Setup Using Two Single Ended Connections Pre-Emphasis Level Tests (A Minus B Configuration) You can use any oscilloscope channel and connect it to any lane test point. You select the channels used for testing lanes in the Set Up tab of the DisplayPort Electrical Performance Compliance Test Application.
9 Source Pre-Emphasis Level Differential Tests (Normative & Informative) Source Pre-Emphasis Level Differential Tests This test evaluates the effect of pre- Emphasis on the source waveform by measuring the peak differential amplitude and assuring the accuracy of the pre- Emphasis setting. (Reference: Table 3.10 VESA DisplayPort Standard).
9 Source Pre-Emphasis Level Differential Tests (Normative & Informative) of the oscilloscope. If you are using four connections, connect the four probes to four channels of the oscilloscope. 4 Connect the SMA to SMP cable to the SMA probe head of one of the probes and to the data lane connector on the W2641A fixture that you want to test. 5 Connect the other SMA to SMP cable to the other SMA probe head and to the data lane on the W2641A test fixture that you want to test.
9 Source Pre-Emphasis Level Differential Tests (Normative & Informative) Navigate to the Pre- Emphasis Level - Lane # - Pre- Emphasis Level Test or Lane # - Non- Transition Voltage Range Measurement where # is the lane number to be tested. Figure 27 Selecting Pre-Emphasis Level Differential Tests 9 Follow the DisplayPort Electrical Performance Compliance Test Application’s task flow to set up configuration options (see Table 11), make oscilloscope connections, run the tests, and view the test results.
Source Pre-Emphasis Level Differential Tests (Normative & Informative) 9 Table 11 Test Configuration Options Configuration Option Description Clock Recovery Settings Clock Recovery Order Set either a second order PLL or a first order PLL method to recover the clock. Clock Recovery Loop Bandwidth (D10.2) - 1.62 Gbps Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2 pattern is used. Please specify in correct format; xMHz, xkHz or xHz. Clock Recovery Loop Bandwidth (PRBS 7) 1.
9 Source Pre-Emphasis Level Differential Tests (Normative & Informative) Table 11 Test Configuration Options Configuration Option Description Vswing Edge Sets the number of Edges used when performing the Vswing measurement. The Vswing value is used to ensure that the waveform is displayed as large as possible in the waveform viewing area. Increasing this value increases the test run time but improves the repeatability of the measurement.
Source Pre-Emphasis Level Differential Tests (Normative & Informative) 9 PASS Condition The pre- Emphasis calculation must fall within the following ranges for each pre- Emphasis level: 0 dB setting: Resultant > - 8.4 dB 3.5 dB setting: Resultant3.5dB > 2.0 dB 6.0 dB setting: Resultant6.0dB > Resultant3.5dB + 1.6 9.5 dB setting: Resultant9.5dB > Resultant6.0dB + 1.6 The non- transition voltage range measurement calculation must fall within the following ranges: Resultant < 0.
9 86 Source Pre-Emphasis Level Differential Tests (Normative & Informative) Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
U7232A DisplayPort Electrical Performance Compliance Test Application Method of Implementation 10 Source Inter Pair Skew Differential Tests Probing for Source Inter Pair Skew Differential Tests 88 Source Inter Pair Skew Differential Test 90 This section provides the guidelines for source inter pair skew differential tests using an Agilent 8 GHz or greater Infiniium oscilloscope, InfiniiMax probes, and the DisplayPort Electrical Performance Compliance Test Application.
10 Source Inter Pair Skew Differential Tests Probing for Source Inter Pair Skew Differential Tests When performing the inter pair skew test, the DisplayPort Electrical Performance Compliance Test Application will prompt you to make the proper connections. Your DisplayPort test environment setup on the Set Up tab must match the physical connection. Figure 28 and Figure 29 below show the differential and the single- ended connections for Inter Pair Skew Differential Tests..
Source Inter Pair Skew Differential Tests 10 . Infiniium Oscilloscope DUT SMA to SMP cables Data Channel Lane on the W2641A test fixture Figure 29 Differential Measurement Setup Using Two Single Ended Connections - Inter Pair Skew Tests (A Minus B Configuration) You can use any oscilloscope channel and connect it to any lane test point. You select the channels used for testing lanes in the Set Up tab of the DisplayPort Electrical Performance Compliance Test Application.
10 Source Inter Pair Skew Differential Tests Source Inter Pair Skew Differential Test The inter pair skew test evaluates the skew, or time delay, between respective differential data lanes in the DisplayPort interface. (Reference Table 3.10 VESA DisplayPort Standard). The DisplayPort interface has the ability to skew, or deskew lanes by 20 UI (Unit Intervals) which is as much as 12ns (1.62Gb/s) and is intended to eliminate simultaneous degradation of concurrent bytes of transmitted data.
Source Inter Pair Skew Differential Tests 10 Navigate to the Inter Pair Skew - Lane # - Inter Pair Skew Test where # is the lane number to be tested. Figure 30 Selecting Inter Pair Skew Differential Tests 8 Follow the DisplayPort Electrical Performance Compliance Test Application’s task flow to set up configuration options (see Table 12), make oscilloscope connections, run the tests, and view the tests results. Options may vary depending on the selected mode: Compliance Mode or Debug Mode.
10 Source Inter Pair Skew Differential Tests Table 12 Test Configuration Options Configuration Option Description Clock Recovery Settings Clock Recovery Order Set either a second order PLL or a first order PLL method to recover the clock. Clock Recovery Loop Bandwidth (D10.2) - 1.62 Gbps Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2 pattern is used. Please specify in correct format; xMHz, xkHz or xHz. Clock Recovery Loop Bandwidth (PRBS 7) 1.
Source Inter Pair Skew Differential Tests 10 Table 12 Test Configuration Options Configuration Option Description Test Plan Check Mode Turn on test plan check mode to simulate the actual test plan run flow without actual tests being run. SSC Acquisitions Number of SSC cycle captured for SSC related tests. Maximum number is 25. Low Bit Rate SSC Smoothing Points Sets the number of smoothing points for SSC low pass filter when bit rate is 1.62 Gbps.
10 Source Inter Pair Skew Differential Tests Test References See Test 3.4: Inter- Pair Skew Measurement, in the DisplayPort- Compliance Test Specification Version 1.1.
U7232A DisplayPort Electrical Performance Compliance Test Application Method of Implementation 11 Source Unit Interval Differential Tests (Informative) Probing for Source Unit Interval Differential Tests 96 Source Unit Interval Differential Tests 98 This section provides the guidelines for source unit interval differential tests using an Agilent 8 GHz or greater Infiniium oscilloscope, 1168A or 1169A probes, and the DisplayPort Electrical Performance Compliance Test Application.
11 Source Unit Interval Differential Tests (Informative) Probing for Source Unit Interval Differential Tests When performing the unit interval test, the DisplayPort Electrical Performance Compliance Test Application will prompt you to make the proper connections. Your DisplayPort test environment setup on the Set Up tab must match the physical connection. Figure 31 and Figure 32 below show the differential and the single- ended connections for Unit Interval Differential Tests. .
Source Unit Interval Differential Tests (Informative) 11 . Infiniium Oscilloscope DUT SMA to SMP cables Data Channel Lane on the W2641A test fixture Figure 32 Differential Measurement Setup Using Two Single Ended Connections - Unit Interval Tests (A Minus B Configuration) You can use any oscilloscope channel and connect it to any lane test point. You select the channels used for testing lanes in the Set Up tab of the DisplayPort Electrical Performance Compliance Test Application.
11 Source Unit Interval Differential Tests (Informative) Source Unit Interval Differential Tests Unit interval test evaluates the overall variation in the UI width over at least one full typical SSC cycle to ensure it stays within the specification limit. This test calculates the average unit interval with and without the spread spectrum clocking which will have very little to do with interoperability unless the unit interval is at the extremes.
Source Unit Interval Differential Tests (Informative) 11 Navigate to the Unit Interval - Lane # - SSC Unit Interval Test where # is the lane number to be tested. Figure 33 Selecting Unit Interval Differential Tests 9 Follow the DisplayPort Electrical Performance Compliance Test Application’s task flow to set up configuration options (see Table 13), make oscilloscope connections, run the tests, and view the tests results. Options may vary depending on the selected mode: Compliance Mode or Debug Mode.
11 Source Unit Interval Differential Tests (Informative) Table 13 Test Configuration Options Configuration Option Description Clock Recovery Settings Clock Recovery Order Set either a second order PLL or a first order PLL method to recover the clock. Clock Recovery Loop Bandwidth (D10.2) - 1.62 Gbps Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2 pattern is used. Please specify in correct format; xMHz, xkHz or xHz. Clock Recovery Loop Bandwidth (PRBS 7) 1.
11 Source Unit Interval Differential Tests (Informative) Table 13 Test Configuration Options Configuration Option Description Test Plan Check Mode Turn on test plan check mode to simulate the actual test plan run flow without actual tests being run. SSC Acquisitions Number of SSC cycle captured for SSC related tests. Maximum number is 25. Low Bit Rate SSC Smoothing Points Sets the number of smoothing points for SSC low pass filter when bit rate is 1.62 Gbps.
11 Source Unit Interval Differential Tests (Informative) Test References See section 3.6, in the DisplayPort- Compliance Test Specification Version 1.1.
U7232A DisplayPort Electrical Performance Compliance Test Application Method of Implementation 12 Source Main Link Frequency Compliance Differential Tests Probing for Source Main Link Frequency Compliance Differential Tests 104 Source Main Link Frequency Compliance Differential Tests 106 This section provides the guidelines for the source main link frequency compliance tests using an Agilent 8 GHz or greater Infiniium oscilloscope, InfiniiMax probes, and the DisplayPort Electrical Performance Compliance T
12 Source Main Link Frequency Compliance Differential Tests Probing for Source Main Link Frequency Compliance Differential Tests When performing the source main link frequency compliance tests, the DisplayPort Electrical Performance Compliance Test Application will prompt you to make the proper connections. Your DisplayPort test environment setup on the Set Up tab must match the physical connection.
Source Main Link Frequency Compliance Differential Tests 12 . Infiniium Oscilloscope DUT SMA to SMP cables Data Channel Lane on the W2641A test fixture Figure 35 Differential Measurement Setup Using Two Single Ended Connections - Main Link Frequency Compliance Tests (A Minus B Configuration) You can use any oscilloscope channel and connect it to any lane test point. You select the channels used for testing lanes in the Set Up tab of the DisplayPort Electrical Performance Compliance Test Application.
12 Source Main Link Frequency Compliance Differential Tests Source Main Link Frequency Compliance Differential Tests The main link frequency compliance test evaluates the overall variation in source time base accuracy, ensuring the device stays within the required +- 300 PPM limit. Tests shall be performed on a PRBS 7 signal with SSC disabled. An evaluation of at least 10 acquisitions is required.
12 Source Main Link Frequency Compliance Differential Tests Navigate to the Main Link Frequency Compliance - Lane # - Main Link Frequency Compliance where # is the lane number to be tested. Figure 36 Selecting Main Link Frequency Compliance Tests 8 Follow the DisplayPort Electrical Performance Compliance Test Application’s task flow to set up configuration options (see Table 14), make oscilloscope connections, run the tests, and view the tests results.
12 Source Main Link Frequency Compliance Differential Tests Table 14 Test Configuration Options Configuration Option Description Clock Recovery Settings Clock Recovery Order Set either a second order PLL or a first order PLL method to recover the clock. Clock Recovery Loop Bandwidth (D10.2) - 1.62 Gbps Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2 pattern is used. Please specify in correct format; xMHz, xkHz or xHz. Clock Recovery Loop Bandwidth (PRBS 7) 1.
12 Source Main Link Frequency Compliance Differential Tests Table 14 Test Configuration Options Configuration Option Description Test Plan Check Mode Turn on test plan check mode to simulate the actual test plan run flow without actual tests being run. SSC Acquisitions Number of SSC cycle captured for SSC related tests. Maximum number is 25. Low Bit Rate SSC Smoothing Points Sets the number of smoothing points for SSC low pass filter when bit rate is 1.62 Gbps.
12 Source Main Link Frequency Compliance Differential Tests 110 Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
U7232A DisplayPort Electrical Performance Compliance Test Application Method of Implementation 13 Source Spread Spectrum Clocking (SSC) Differential Tests (Normative & Informative) Probing for Source Spread Spectrum Clocking (SSC) Differential Tests 112 Source Spread Spectrum Clocking (SSC) Differential Test 114 This section provides the guidelines for the source spread spectrum clocking (SSC) differential tests using an Agilent 8 GHz or greater Infiniium oscilloscope, 1168A or 1169A probes, and the Displ
13 Source Spread Spectrum Clocking (SSC) Differential Tests (Normative & Informative) Probing for Source Spread Spectrum Clocking (SSC) Differential Tests When performing the spread spectrum clocking (SSC) test, the DisplayPort Electrical Performance Compliance Test Application will prompt you to make the proper connections. Your DisplayPort test environment setup on the Set Up tab must match the physical connection.
Source Spread Spectrum Clocking (SSC) Differential Tests (Normative & Informative) 13 . Infiniium Oscilloscope DUT SMA to SMP cables Data Channel Lane on the W2641A test fixture Figure 38 Differential Measurement Setup Using Two Single Ended Connections - SSC Tests (A Minus B Configuration) You can use any oscilloscope channel and connect it to any lane test point. You select the channels used for testing lanes in the Set Up tab of the DisplayPort Electrical Performance Compliance Test Application.
13 Source Spread Spectrum Clocking (SSC) Differential Tests (Normative & Informative) Source Spread Spectrum Clocking (SSC) Differential Test Spread Spectrum Modulation Frequency (Normative) The spread spectrum modulation frequency evaluates the frequency of the SSC modulation and validates if it falls with specification limits. The SSC frequency will be evaluated at the highest bit rate the transmitter supports. Tests shall be performed on a PRBS 7 signal, with SSC enabled.
13 Source Spread Spectrum Clocking (SSC) Differential Tests (Normative & Informative) Test Procedure 1 Start the automated testing application as described in “Starting the DisplayPort Electrical Performance Compliance Test Application" on page 22. 2 Connect the W2641A test fixture or other appropriate fixture to the device under test (DUT). 3 If you are using one connection, connect the probe to one channel. If you are using two connections, connect the two probes to two channels of the oscilloscope.
13 Source Spread Spectrum Clocking (SSC) Differential Tests (Normative & Informative) Navigate to the Spread Spectrum Clocking (SSC) group and select the appropriate test and the lane number to be tested. Figure 39 Selecting the Spread Spectrum Clocking (SSC) Tests 9 Follow the DisplayPort Electrical Performance Compliance Test Application’s task flow to set up configuration options (see Table 15), run the test and view the test results.
Source Spread Spectrum Clocking (SSC) Differential Tests (Normative & Informative) 13 Table 15 Test Configuration Options Configuration Option Description Clock Recovery Settings Clock Recovery Order Set either a second order PLL or a first order PLL method to recover the clock. Clock Recovery Loop Bandwidth (D10.2) - 1.62 Gbps Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2 pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
13 Source Spread Spectrum Clocking (SSC) Differential Tests (Normative & Informative) Table 15 Test Configuration Options Configuration Option Description Vswing Edge Sets the number of Edges used when performing the Vswing measurement. The Vswing value is used to ensure that the waveform is displayed as large as possible in the waveform viewing area. Increasing this value increases the test run time but improves the repeatability of the measurement.
Source Spread Spectrum Clocking (SSC) Differential Tests (Normative & Informative) 13 Test Pattern: D10.2. SSC: Enabled. The devices that do not have SSC Enabled will not be tested. An evaluation of at least 10 full SSC cycle is required. SSC Deviation HF Variation Test Condition Bit Rate: highest rates are supported. Output Level: 800 mVolts. Pre- Emphasis: 0 dB. Test Pattern: D10.2. SSC: Enabled. The devices that do not have SSC Enabled will not be tested.
13 Source Spread Spectrum Clocking (SSC) Differential Tests (Normative & Informative) Test References See Test 3.15: Spread Spectrum Modulation Frequency, Test 3.16: Spread Spectrum Modulation Deviation and Test 3.17: Deviation HF Variation in the DisplayPort- Compliance Test Specification Version 1.1.
U7232A DisplayPort Electrical Performance Compliance Test Application Method of Implementation 14 Source Rise-Fall Mismatch Single-Ended Tests (Informative) Probing for Source Rise-Fall Mismatch Single-Ended Tests 122 Source Rise-Fall Mismatch Single-Ended Tests 123 This section provides the guidelines for source rise- fall mismatch single- ended tests using an Agilent 8 GHz or greater Infiniium oscilloscope, 1168A or 1169A probes, and the DisplayPort Electrical Performance Compliance Test Application.
14 Source Rise-Fall Mismatch Single-Ended Tests (Informative) Probing for Source Rise-Fall Mismatch Single-Ended Tests When performing the rise- fall mismatch test, the DisplayPort Electrical Performance Compliance Test Application will prompt you to make the proper connections. Your DisplayPort test environment setup on the Set Up tab must match the physical connection. Figure 40 below shows the single- ended connections for the Rise- Fall Mismatch Single- Ended Tests. .
14 Source Rise-Fall Mismatch Single-Ended Tests (Informative) Source Rise-Fall Mismatch Single-Ended Tests The rise and fall time mismatch tests evaluate the differences in rise and fall times of the two single- ended waveform in a given differential data lane of a DisplayPort interface. (Reference Table 3.10 VESA DisplayPort Standard specification).
14 Source Rise-Fall Mismatch Single-Ended Tests (Informative) Navigate to the Rise- Fall Mismatch group, and check the Rising Mismatch or Falling Mismatch tests that you want to perform and the lane number to be tested. Figure 41 Selecting Rise-Fall Mismatch Tests 9 Follow the DisplayPort Electrical Performance Compliance Test Application’s task flow to set up configuration options (see Table 16), make oscilloscope connections, run the tests, and view the tests results.
14 Source Rise-Fall Mismatch Single-Ended Tests (Informative) Table 16 Test Configuration Options Configuration Option Description Clock Recovery Settings Clock Recovery Order Set either a second order PLL or a first order PLL method to recover the clock. Clock Recovery Loop Bandwidth (D10.2) - 1.62 Gbps Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2 pattern is used. Please specify in correct format; xMHz, xkHz or xHz. Clock Recovery Loop Bandwidth (PRBS 7) 1.
14 Source Rise-Fall Mismatch Single-Ended Tests (Informative) Table 16 Test Configuration Options Configuration Option Description Test Plan Check Mode Turn on test plan check mode to simulate the actual test plan run flow without actual tests being run. SSC Acquisitions Number of SSC cycle captured for SSC related tests. Maximum number is 25. Low Bit Rate SSC Smoothing Points Sets the number of smoothing points for SSC low pass filter when bit rate is 1.62 Gbps.
Source Rise-Fall Mismatch Single-Ended Tests (Informative) 14 Test References See section 3.7, in the DisplayPort- Compliance Test Specification Version 1.1.
14 Source Rise-Fall Mismatch Single-Ended Tests (Informative) 128 Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
U7232A DisplayPort Electrical Performance Compliance Test Application Method of Implementation 15 Source Intra Pair Skew Single-Ended Tests Probing for Source Intra Pair Skew Single-Ended Tests 130 Source Intra Pair Skew Single-Ended Tests 131 This section provides the guidelines for source intra pair skew sing le- ended tests using an A gilent 8 GHz or g reater Inf iniium oscilloscope, InfiniiMax probes, and the DisplayPort Electrical Performance Compliance Test Application.
15 Source Intra Pair Skew Single-Ended Tests Probing for Source Intra Pair Skew Single-Ended Tests When performing the intra pair skew test, the DisplayPort Electrical Performance Compliance Test Application will prompt you to make the proper connections. Your DisplayPort test environment setup on the Set Up tab must match the physical connection. Figure 42 below shows the single- ended connections for Intra Pair Skew Single- Ended Tests. .
15 Source Intra Pair Skew Single-Ended Tests Source Intra Pair Skew Single-Ended Tests The intra pair skew test evaluates the skew, or time delay, between the respective sides of a differential data lane in a DisplayPort interface. (Reference Table 3.10 VESA DisplayPort Standard). Intra pair skew has deleterious effects on signal rise time and manner of crossing through the transition point. The DisplayPort specification at package pins (TP1) is 20 ps.
15 Source Intra Pair Skew Single-Ended Tests Navigate to the Intra Pair Skew - Lane # - Intra Pair Skew Test where # is the lane number to be tested. Figure 43 Selecting Intra Pair Skew Tests 8 Follow the DisplayPort Electrical Performance Compliance Test Application’s task flow to set up configuration options (see Table 17), make oscilloscope connections, run the tests, and view the tests results. Options may vary depending on the selected mode: Compliance Mode or Debug Mode.
15 Source Intra Pair Skew Single-Ended Tests Table 17 Test Configuration Options Configuration Option Description Clock Recovery Settings Clock Recovery Order Set either a second order PLL or a first order PLL method to recover the clock. Clock Recovery Loop Bandwidth (D10.2) - 1.62 Gbps Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2 pattern is used. Please specify in correct format; xMHz, xkHz or xHz. Clock Recovery Loop Bandwidth (PRBS 7) 1.
15 Source Intra Pair Skew Single-Ended Tests Table 17 Test Configuration Options Configuration Option Description Test Plan Check Mode Turn on test plan check mode to simulate the actual test plan run flow without actual tests being run. SSC Acquisitions Number of SSC cycle captured for SSC related tests. Maximum number is 25. Low Bit Rate SSC Smoothing Points Sets the number of smoothing points for SSC low pass filter when bit rate is 1.62 Gbps.
Source Intra Pair Skew Single-Ended Tests Agilent U7232A DisplayPort Electrical Performance Compliance Test Application 15 135
15 Source Intra Pair Skew Single-Ended Tests 136 Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
U7232A DisplayPort Electrical Performance Compliance Test Application Method of Implementation 16 Source AC Common Mode Noise Single-Ended Tests Probing for Source AC Common Mode Noise Single-Ended Tests 138 Source AC Common Mode Noise Single-Ended Test 139 This section provides the guidelines for source AC common mode noise single- ended tests using an Agilent 8 GHz or greater Infiniium oscilloscope, InfiniiMax probes, and the DisplayPort Electrical Performance Compliance Test Application.
16 Source AC Common Mode Noise Single-Ended Tests Probing for Source AC Common Mode Noise Single-Ended Tests When performing the AC common mode noise test, the DisplayPort Electrical Performance Compliance Test Application will prompt you to make the proper connections. Your DisplayPort test environment setup on the Set Up tab must match the physical connection. Figure 44 below shows the single- ended connections for AC Common Mode Noise Single- Ended Tests. .
16 Source AC Common Mode Noise Single-Ended Tests Source AC Common Mode Noise Single-Ended Test The AC common mode noise measurement of the distributed clock network verifies that the nominal operating clock frequency is within the acceptable tolerance range. In order for the sink devices to properly recover the data, the source clock must operate within the acceptable tolerance range. The test must be made at all bit rates supported by the device under test without pre- Emphasis and a voltage swing of 1.
16 Source AC Common Mode Noise Single-Ended Tests Navigate to the AC Common Mode - Lane # - Common Mode AC Test where # is the lane number to be tested. Figure 45 Selecting AC Common Mode Tests 8 Follow the DisplayPort Electrical Performance Compliance Test Application’s task flow to set up configuration options (see Table 18), make oscilloscope connections, run the tests, and view the tests results. Options may vary depending on the selected mode: Compliance Mode or Debug Mode.
16 Source AC Common Mode Noise Single-Ended Tests Table 18 Test Configuration Options Configuration Option Description Clock Recovery Settings Clock Recovery Order Set either a second order PLL or a first order PLL method to recover the clock. Clock Recovery Loop Bandwidth (D10.2) - 1.62 Gbps Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2 pattern is used. Please specify in correct format; xMHz, xkHz or xHz. Clock Recovery Loop Bandwidth (PRBS 7) 1.
16 Source AC Common Mode Noise Single-Ended Tests Table 18 Test Configuration Options Configuration Option Description Test Plan Check Mode Turn on test plan check mode to simulate the actual test plan run flow without actual tests being run. SSC Acquisitions Number of SSC cycle captured for SSC related tests. Maximum number is 25. Low Bit Rate SSC Smoothing Points Sets the number of smoothing points for SSC low pass filter when bit rate is 1.62 Gbps.
Source AC Common Mode Noise Single-Ended Tests 16 PASS Condition AC Common Mode Noise < 20 mVrms. Test References See Test 3.10: AC Common Mode Noise, in the DisplayPort- Compliance Test Specification Version 1.1.
16 Source AC Common Mode Noise Single-Ended Tests 144 Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
U7232A DisplayPort Electrical Performance Compliance Test Application Method of Implementation 17 Link Layer Protocol Tests Probing for Link Layer Protocol Tests 146 Link Layer Protocol Tests 147 This section provides the guidelines for link layer protocol tests using an Agilent 8 GHz or greater Infiniium oscilloscope, InfiniiMax probes, and the DisplayPort Electrical Performance Compliance Test Application. Link layer protocol tests are not compliance tests.
17 Link Layer Protocol Tests Probing for Link Layer Protocol Tests When performing the link layer protocol test, the DisplayPort Electrical Performance Compliance Test Application will prompt you to make the proper connections. Your DisplayPort test environment setup on the Set Up tab must match the physical connection. Figure 46 below shows the single- ended connections for Link Layer Protocol Tests.
Link Layer Protocol Tests 17 Link Layer Protocol Tests The link layer protocol tests consists of Pre- Emphasis, Level and Bit Rate tests. Link Layer Protocol - Pre-Emphasis The link layer - pre- Emphasis test verifies if the pre- Emphasis of the DUT can change accordingly from the lowest pre- Emphasis to the highest pre- Emphasis setting. The test must be made on the highest bit rate supported by the differential voltage swings of 400 mV using a test pattern of PRBS 7.
17 Link Layer Protocol Tests The test must be made at all bit rates supported by the DUT without pre- Emphasis and a voltage swing of 400 mV. A test pattern of PRBS 7 should be used. Test Procedure 1 Start the automated testing application as described in “Starting the DisplayPort Electrical Performance Compliance Test Application" on page 22. 2 Connect the W2641A test fixture or other appropriate fixture to the device under test (DUT).
Link Layer Protocol Tests 17 Navigate to the Link Layer (Protocol Test) group, and check the test and lane you want to test. Figure 47 Selecting Link Layer Protocol Tests 8 Follow the DisplayPort Electrical Performance Compliance Test Application’s task flow to set up configuration options (see Table 19), make oscilloscope connections, run the tests, and view the tests results. Options may vary depending on the selected mode: Compliance Mode or Debug Mode.
17 Link Layer Protocol Tests Table 19 Test Configuration Options Configuration Option Description Clock Recovery Settings Clock Recovery Order Set either a second order PLL or a first order PLL method to recover the clock. Clock Recovery Loop Bandwidth (D10.2) - 1.62 Gbps Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2 pattern is used. Please specify in correct format; xMHz, xkHz or xHz. Clock Recovery Loop Bandwidth (PRBS 7) 1.
17 Link Layer Protocol Tests Table 19 Test Configuration Options Configuration Option Description Test Plan Check Mode Turn on test plan check mode to simulate the actual test plan run flow without actual tests being run. SSC Acquisitions Number of SSC cycle captured for SSC related tests. Maximum number is 25. Low Bit Rate SSC Smoothing Points Sets the number of smoothing points for SSC low pass filter when bit rate is 1.62 Gbps.
17 Link Layer Protocol Tests Pre-Emphasis PASS Condition Link Layer Protocol - Pre- Emphasis Test For 3.5 dB setting: Resultant3.5dB > 2.0 dB For 6.0 dB setting: Resultant6.0dB results > Resultant3.5dB + 1.6 For 9.5 dB setting: Resultant9.5dB results > Resultant6.0dB + 1.
U7232A DisplayPort Electrical Performance Compliance Test Application Method of Implementation 18 Sink Eye Diagram Tests Probing for Sink Eye Diagram Tests 154 Sink Eye Diagram Tests 156 This section provides the guidelines for sink eye diagram tests using an Agilent 8 GHz or greater Infiniium oscilloscope, 1168A or 1169A probes, and the DisplayPort Electrical Performance Compliance Test Application.
18 Sink Eye Diagram Tests Probing for Sink Eye Diagram Tests When performing the sink eye diagram test, the DisplayPort Electrical Performance Compliance Test Application will prompt you to make the proper connections. Your DisplayPort test environment setup on the Set Up tab must match the physical connection. Figure 48 and Figure 49 show a physical connection for making differential and single- ended connections. . Infiniium Oscilloscope N5380A SMA probe head.
18 Sink Eye Diagram Tests . Infiniium Oscilloscope DUT SMA to SMP cables Data Channel Lane on the W2641A test fixture Figure 49 Differential Measurement Setup Using Two Single Ended Connections - Sink Eye Diagram Tests (A Minus B Configuration) You can use any oscilloscope channel and connect it to any lane test point. You select the channels used for testing lanes in the Set Up tab of the DisplayPort Electrical Performance Compliance Test Application.
18 Sink Eye Diagram Tests Sink Eye Diagram Tests The eye diagram test provides a visual evaluation of the amplitude and timing variations of the waveform with the overall objective of obtaining a specified bit error rate in the transmitted data. The test must use a PRBS 7 test pattern at all voltage levels. The test should be performed without pre- Emphasis.
Sink Eye Diagram Tests 18 Navigate to the Eye Diagram Test - Lane # - Sink Eye Diagram Test where # is the lane number to be tested. Figure 50 Selecting Sink Eye Diagram Tests 8 Follow the DisplayPort Electrical Performance Compliance Test Application’s task flow to set up configuration options (see Table 20), run the test and view the test results. Options may vary depending on selected mode: Compliance Mode or Debug Mode.
18 Sink Eye Diagram Tests Table 20 Test Configuration Options Configuration Option Description Clock Recovery Settings Clock Recovery Order Set either a second order PLL or a first order PLL method to recover the clock. Clock Recovery Loop Bandwidth (D10.2) - 1.62 Gbps Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2 pattern is used. Please specify in correct format; xMHz, xkHz or xHz. Clock Recovery Loop Bandwidth (PRBS 7) 1.
18 Sink Eye Diagram Tests Table 20 Test Configuration Options Configuration Option Description Test Plan Check Mode Turn on test plan check mode to simulate the actual test plan run flow without actual tests being run. SSC Acquisitions Number of SSC cycle captured for SSC related tests. Maximum number is 25. Low Bit Rate SSC Smoothing Points Sets the number of smoothing points for SSC low pass filter when bit rate is 1.62 Gbps.
18 Sink Eye Diagram Tests Figure 51 Selecting User Defined File for the Sink Equalizer 160 Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
Sink Eye Diagram Tests 18 Figure 52 Selecting User Defined File 10 The following select file dialog box appears. Select your coefficient file (*.equ) and click Open. The test will run based on the your user defined coefficient file. PASS Condition The following table and figure define the mask for the eye measurements. There can be no signal trajectories entering into the mask. Table 21 shows the voltage and time coordinates for the mask used for the eye diagram.
18 Sink Eye Diagram Tests Table 21 Sink Eye Vertices for TP3 Bit Rate Mask Point Reduced (1.6 Gb/s) High (2.7 Gb/s) 1 0.375, 0.000 0.246, 0.000 2 0.500, 0.023 0.500, 0.075 3 0.625, 0.000 0.755, 0.000 4 0.500, -0.023 0.500, -0.075 Figure 53 The Sink Eye Mask at TP3 Mask Test: Zero mask failures. Test References See Test 3.1: Eye Diagram Testing, in the DisplayPort- Compliance Test Specification Version 1.1.
U7232A DisplayPort Electrical Performance Compliance Test Application Method of Implementation 19 Sink Total Jitter Tests Probing for Sink Total Jitter Tests 164 Sink Total Jitter Tests 166 This section provides the guidelines for sink total jitter tests using an Agilent 8 GHz or greater Infiniium oscilloscope, InfiniiMax probes, and the DisplayPort Electrical Performance Compliance Test Application.
19 Sink Total Jitter Tests Probing for Sink Total Jitter Tests When performing the sink total jitter test, the DisplayPort Electrical Performance Compliance Test Application will prompt you to make the proper connections. Your DisplayPort test environment setup on the Set Up tab must match the physical connection. Figure 54 and Figure 55 show a physical connection for making differential and single- ended connections. . Infiniium Oscilloscope N5380A SMA probe head.
19 Sink Total Jitter Tests . Infiniium Oscilloscope DUT SMA to SMP cables Data Channel Lane on the W2641A test fixture Figure 55 Differential Measurement Setup Using Two Single Ended Connections - Sink Total Jitter Tests (A Minus B Configuration) You can use any oscilloscope channel and connect it to any lane test point. You select the channels used for testing lanes in the Set Up tab of the DisplayPort Electrical Performance Compliance Test Application.
19 Sink Total Jitter Tests Sink Total Jitter Tests To evaluate the total jitter accompanying the data transmission at either an explicit bit error rate of 10- 9 or through an approved estimation technique. This measurement is a data time interval error (Data- TIE) jitter measurement. (Reference: Table 3.13 VESA DisplayPort Standard). The overall system jitter budget allocates different amounts of jitter which each component of the system is allowed to contribute.
Sink Total Jitter Tests 19 Navigate to the Total Jitter Test - Lane # - Sink Total Jitter Test where # is the lane number to be tested. Figure 56 Selecting Sink Total Jitter Tests 8 Follow the DisplayPort Electrical Performance Compliance Test Application’s task flow to set up configuration options (see Table 22), run the test and view the test results. Options may vary depending on selected mode: Compliance Mode or Debug Mode.
19 Sink Total Jitter Tests Table 22 Test Configuration Options Configuration Option Description Clock Recovery Settings Clock Recovery Order Set either a second order PLL or a first order PLL method to recover the clock. Clock Recovery Loop Bandwidth (D10.2) - 1.62 Gbps Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2 pattern is used. Please specify in correct format; xMHz, xkHz or xHz. Clock Recovery Loop Bandwidth (PRBS 7) 1.
19 Sink Total Jitter Tests Table 22 Test Configuration Options Configuration Option Description Test Plan Check Mode Turn on test plan check mode to simulate the actual test plan run flow without actual tests being run. SSC Acquisitions Number of SSC cycle captured for SSC related tests. Maximum number is 25. Low Bit Rate SSC Smoothing Points Sets the number of smoothing points for SSC low pass filter when bit rate is 1.62 Gbps.
19 Sink Total Jitter Tests Figure 57 Selecting User Defined File for the Sink Equalizer 170 Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
Sink Total Jitter Tests 19 Figure 58 Selecting User Defined File 10 The following select file dialog box appears. Select your coefficient file (*.equ) and click Open. The test will run based on the your user defined coefficient file. PASS Condition - Test References See Test 3.12: Total Jitter (TJ) Measurements in the DisplayPort- Compliance Test Specification Version 1.1.
19 Sink Total Jitter Tests 172 Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
U7232A DisplayPort Electrical Performance Compliance Test Application Method of Implementation 20 Sink Non-ISI Jitter Tests Probing for Sink Non-ISI Jitter Tests 174 Sink Non-ISI Jitter Tests 176 This section provides the guidelines for sink non- ISI jitter tests using an Agilent 8 GHz or greater Infiniium oscilloscope, InfiniiMax probes, and the DisplayPort Electrical Performance Compliance Test Application.
20 Sink Non-ISI Jitter Tests Probing for Sink Non-ISI Jitter Tests When performing the sink non- ISI jitter test, the DisplayPort Electrical Performance Compliance Test Application will prompt you to make the proper connections. Your DisplayPort test environment setup on the Set Up tab must match the physical connection. Figure 59 and Figure 60 show a physical connection for making differential and single- ended connections. . Infiniium Oscilloscope N5380A SMA probe head.
20 Sink Non-ISI Jitter Tests . Infiniium Oscilloscope DUT SMA to SMP cables Data Channel Lane on the W2641A test fixture Figure 60 Differential Measurement Setup Using Two Single Ended Connections - Sink Non-ISI Jitter Tests (A Minus B Configuration) You can use any oscilloscope channel and connect it to any lane test point. You select the channels used for testing lanes in the Set Up tab of the DisplayPort Electrical Performance Compliance Test Application.
20 Sink Non-ISI Jitter Tests Sink Non-ISI Jitter Tests To evaluate the Non- ISI jitter accompanying the data transmission at either an explicit bit error rate of 10- 9 or through an approved estimation technique. (Reference: Table 3.13 VESA DisplayPort Standard). The overall system jitter budget allocates different amounts of jitter which each component of the system is allowed to contribute. To exceed any of these limits is to violate the component level jitter budget.
Sink Non-ISI Jitter Tests 20 Navigate to the Non- ISI Jitter Test - Lane # - Non- ISI Jitter Test where # is the lane number to be tested. Figure 61 Selecting Sink Non-Jitter Tests 8 Follow the DisplayPort Electrical Performance Compliance Test Application’s task flow to set up configuration options (see Table 23), run the test and view the test results. Options may vary depending on selected mode: Compliance Mode or Debug Mode.
20 Sink Non-ISI Jitter Tests Table 23 Test Configuration Options Configuration Option Description Clock Recovery Settings Clock Recovery Order Set either a second order PLL or a first order PLL method to recover the clock. Clock Recovery Loop Bandwidth (D10.2) - 1.62 Gbps Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2 pattern is used. Please specify in correct format; xMHz, xkHz or xHz. Clock Recovery Loop Bandwidth (PRBS 7) 1.
20 Sink Non-ISI Jitter Tests Table 23 Test Configuration Options Configuration Option Description Test Plan Check Mode Turn on test plan check mode to simulate the actual test plan run flow without actual tests being run. SSC Acquisitions Number of SSC cycle captured for SSC related tests. Maximum number is 25. Low Bit Rate SSC Smoothing Points Sets the number of smoothing points for SSC low pass filter when bit rate is 1.62 Gbps.
20 Sink Non-ISI Jitter Tests Figure 62 Selecting User Defined File for the Sink Equalizer 180 Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
Sink Non-ISI Jitter Tests 20 Figure 63 Selecting User Defined File 10 The following select file dialog box appears. Select your coefficient file (*.equ) and click Open. The test will run based on the your user defined coefficient file. PASS Condition Table 24 Non-ISI Jitter at Internal and Compliance Points. Receiver package pin Transmitter Connector (TP2) High-bit Rate (2.7 Gb/s per lane) Ap-p 0.339 UI 0.330 UI Reduced-bit Rate (1.62 Gb/s per lane) Ap-p 0.465 UI 0.442 UI UI is Unit Interval.
20 Sink Non-ISI Jitter Tests Test References See Test 3.12: Non- ISI Jitter (TJ) Measurements in the DisplayPort- Compliance Test Specification Version 1.1.
U7232A DisplayPort Electrical Performance Compliance Test Application Method of Implementation 21 Cable Eye Diagram Tests Probing for Cable Eye Diagram Tests 184 Cable Eye Diagram Tests 186 This section provides the guidelines for cable eye diagram tests using an Agilent 8 GHz or greater Infiniium oscilloscope, 1168A or 1169A probes, and the DisplayPort Electrical Performance Compliance Test Application.
21 Cable Eye Diagram Tests Probing for Cable Eye Diagram Tests When performing the cable eye diagram test, the DisplayPort Electrical Performance Compliance Test Application will prompt you to make the proper connections. Your DisplayPort test environment setup on the Set Up tab must match the physical connection. Figure 64 and Figure 65 show a physical connection for making differential and single- ended connections. .
Cable Eye Diagram Tests 21 . Infiniium Oscilloscope DUT SMA to SMP cables Data Channel Lane on the W2641A test fixture Figure 65 Differential Measurement Setup Using Two Single Ended Connections - Cable Eye Diagram Tests (A Minus B Configuration) You can use any oscilloscope channel and connect it to any lane test point. You select the channels used for testing lanes in the Set Up tab of the DisplayPort Electrical Performance Compliance Test Application.
21 Cable Eye Diagram Tests Cable Eye Diagram Tests The eye diagram test provides a visual evaluation of the amplitude and timing variations of the waveform with the overall objective of obtaining a specified bit error rate in transmitted data. The test must use a PRBS 7 test pattern at all voltage levels. The test should be performed without pre- Emphasis.
Cable Eye Diagram Tests 21 Navigate to the Eye Diagram Test - Lane # - Cable Eye Diagram Test where # is the lane number to be tested. Figure 66 Selecting Cable Eye Diagram Tests 8 Follow the DisplayPort Electrical Performance Compliance Test Application’s task flow to set up configuration options (see Table 25), run the test and view the test results. Options may vary depending on selected mode: Compliance Mode or Debug Mode.
21 Cable Eye Diagram Tests Table 25 Test Configuration Options Configuration Option Description Clock Recovery Settings Clock Recovery Order Set either a second order PLL or a first order PLL method to recover the clock. Clock Recovery Loop Bandwidth (D10.2) - 1.62 Gbps Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2 pattern is used. Please specify in correct format; xMHz, xkHz or xHz. Clock Recovery Loop Bandwidth (PRBS 7) 1.
21 Cable Eye Diagram Tests Table 25 Test Configuration Options Configuration Option Description Test Plan Check Mode Turn on test plan check mode to simulate the actual test plan run flow without actual tests being run. SSC Acquisitions Number of SSC cycle captured for SSC related tests. Maximum number is 25. Low Bit Rate SSC Smoothing Points Sets the number of smoothing points for SSC low pass filter when bit rate is 1.62 Gbps.
21 Cable Eye Diagram Tests Figure 67 Selecting User Defined File for the Cable Equalizer 190 Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
Cable Eye Diagram Tests 21 Figure 68 Selecting User Defined File 10 The following select file dialog box appears. Select your coefficient file (*.equ) and click Open. The test will run based on the your user defined coefficient file. PASS Condition The following table and figure define the mask for the eye measurements. There can be no signal trajectories entering into the mask. Table 26 shows the voltage and time coordinates for the mask used for the eye diagram.
21 Cable Eye Diagram Tests Table 26 Cable Eye Vertices for TP3 Bit Rate Mask Point Reduced (1.6 Gb/s) High (2.7 Gb/s) 1 0.375, 0.000 0.246, 0.000 2 0.500, 0.023 0.500, 0.075 3 0.625, 0.000 0.755, 0.000 4 0.500, -0.023 0.500, -0.075 Figure 69 The Cable Eye Mask at TP3 Mask Test: Zero mask failures. Test References See Test 3.1: Eye Diagram Testing, in the DisplayPort- Compliance Test Specification Version 1.
U7232A DisplayPort Electrical Performance Compliance Test Application Method of Implementation 22 Cable Total Jitter Tests Probing for Cable Total Jitter Tests 194 Cable Total Jitter Tests 196 This section provides the guidelines for cable total jitter tests using an Agilent 8 GHz or greater Infiniium oscilloscope, InfiniiMax probes, and the DisplayPort Electrical Performance Compliance Test Application.
22 Cable Total Jitter Tests Probing for Cable Total Jitter Tests When performing the cable total jitter test, the DisplayPort Electrical Performance Compliance Test Application will prompt you to make the proper connections. Your DisplayPort test environment setup on the Set Up tab must match the physical connection. Figure 70 and Figure 71 show a physical connection for making differential and single- ended connections. .
Cable Total Jitter Tests 22 . Infiniium Oscilloscope DUT SMA to SMP cables Data Channel Lane on the W2641A test fixture Figure 71 Differential Measurement Setup Using Two Single Ended Connections - Cable Total Jitter Tests (A Minus B Configuration) You can use any oscilloscope channel and connect it to any lane test point. You select the channels used for testing lanes in the Set Up tab of the DisplayPort Electrical Performance Compliance Test Application.
22 Cable Total Jitter Tests Cable Total Jitter Tests To evaluate the total jitter accompanying the data transmission at either an explicit bit error rate of 10- 9 or through an approved estimation technique. This measurement is a data time interval error (Data- TIE) jitter measurement. (Reference: Table 3.13 VESA DisplayPort Standard). The overall system jitter budget allocates different amounts of jitter which each component of the system is allowed to contribute.
Cable Total Jitter Tests 22 Navigate to the Total Jitter Test - Lane # - Cable Total Jitter Test where # is the lane number to be tested. Figure 72 Selecting Cable Total Jitter Tests 8 Follow the DisplayPort Electrical Performance Compliance Test Application’s task flow to set up configuration options (see Table 27), run the test and view the test results. Options may vary depending on selected mode: Compliance Mode or Debug Mode.
22 Cable Total Jitter Tests Table 27 Test Configuration Options Configuration Option Description Clock Recovery Settings Clock Recovery Order Set either a second order PLL or a first order PLL method to recover the clock. Clock Recovery Loop Bandwidth (D10.2) - 1.62 Gbps Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2 pattern is used. Please specify in correct format; xMHz, xkHz or xHz. Clock Recovery Loop Bandwidth (PRBS 7) 1.
22 Cable Total Jitter Tests Table 27 Test Configuration Options Configuration Option Description Test Plan Check Mode Turn on test plan check mode to simulate the actual test plan run flow without actual tests being run. SSC Acquisitions Number of SSC cycle captured for SSC related tests. Maximum number is 25. Low Bit Rate SSC Smoothing Points Sets the number of smoothing points for SSC low pass filter when bit rate is 1.62 Gbps.
22 Cable Total Jitter Tests Figure 73 Selecting User Defined File for the Cable Equalizer 200 Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
Cable Total Jitter Tests 22 Figure 74 Selecting User Defined File 10 The following select file dialog box appears. Select your coefficient file (*.equ) and click Open. The test will run based on the your user defined coefficient file. PASS Condition - Test References See Test 3.12: Total Jitter (TJ) Measurements in the DisplayPort- Compliance Test Specification Version 1.
22 Cable Total Jitter Tests 202 Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
U7232A DisplayPort Electrical Performance Compliance Test Application Method of Implementation 23 Cable Non-ISI Jitter Tests Probing for Cable Non-ISI Jitter Tests 204 Cable Non-ISI Jitter Tests 206 This section provides the guidelines for cable non- ISI jitter tests using an Agilent 8 GHz or greater Infiniium oscilloscope, InfiniiMax probes, and the DisplayPort Electrical Performance Compliance Test Application.
23 Cable Non-ISI Jitter Tests Probing for Cable Non-ISI Jitter Tests When performing the cable non- ISI jitter test, the DisplayPort Electrical Performance Compliance Test Application will prompt you to make the proper connections. Your DisplayPort test environment setup on the Set Up tab must match the physical connection. Figure 75 and Figure 76 show a physical connection for making differential and single- ended connections. . Infiniium Oscilloscope N5380A SMA probe head.
Cable Non-ISI Jitter Tests 23 . Infiniium Oscilloscope DUT SMA to SMP cables Data Channel Lane on the W2641A test fixture Figure 76 Differential Measurement Setup Using Two Single Ended Connections - Cable Non-ISI Jitter Tests (A Minus B Configuration) You can use any oscilloscope channel and connect it to any lane test point. You select the channels used for testing lanes in the Set Up tab of the DisplayPort Electrical Performance Compliance Test Application.
23 Cable Non-ISI Jitter Tests Cable Non-ISI Jitter Tests To evaluate the Non- ISI jitter accompanying the data transmission at either an explicit bit error rate of 10- 9 or through an approved estimation technique. (Reference: Table 3.13 VESA DisplayPort Standard). The overall system jitter budget allocates different amounts of jitter which each component of the system is allowed to contribute. To exceed any of these limits is to violate the component level jitter budget.
23 Cable Non-ISI Jitter Tests Navigate to the Non- ISI Jitter - Lane # - Non- ISI Jitter Test where # is the lane number to be tested. Figure 77 Selecting Cable Non-ISI Jitter Tests 8 Follow the DisplayPort Electrical Performance Compliance Test Application’s task flow to set up configuration options (see Table 28), run the test and view the test results. Options may vary depending on selected mode: Compliance Mode or Debug Mode.
23 Cable Non-ISI Jitter Tests Table 28 Test Configuration Options Configuration Option Description Clock Recovery Settings Clock Recovery Order Set either a second order PLL or a first order PLL method to recover the clock. Clock Recovery Loop Bandwidth (D10.2) - 1.62 Gbps Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2 pattern is used. Please specify in correct format; xMHz, xkHz or xHz. Clock Recovery Loop Bandwidth (PRBS 7) 1.
23 Cable Non-ISI Jitter Tests Table 28 Test Configuration Options Configuration Option Description Test Plan Check Mode Turn on test plan check mode to simulate the actual test plan run flow without actual tests being run. SSC Acquisitions Number of SSC cycle captured for SSC related tests. Maximum number is 25. Low Bit Rate SSC Smoothing Points Sets the number of smoothing points for SSC low pass filter when bit rate is 1.62 Gbps.
23 Cable Non-ISI Jitter Tests Figure 78 Selecting User Defined File for the Cable Equalizer 210 Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
Cable Non-ISI Jitter Tests 23 Figure 79 Selecting User Defined File The following select file dialog box appears. Select your coefficient file (*.equ) and click Open. The test will run based on the your user defined coefficient file PASS Condition Table 29 Non-ISI Jitter at Internal and Compliance Points. Receiver package pin Transmitter Connector (TP2) High-bit Rate (2.7 Gb/s per lane) Ap-p 0.339 UI 0.330 UI Reduced-bit Rate (1.62 Gb/s per lane) Ap-p 0.465 UI 0.442 UI UI is Unit Interval.
23 Cable Non-ISI Jitter Tests Test References See Test 3.12: Non- ISI Jitter (TJ) Measurements in the DisplayPort- Compliance Test Specification Version 1.
U7232A DisplayPort Electrical Performance Compliance Test Application Method of Implementation 24 Calibrating the Infiniium Oscilloscope and Probe Required Equipment for Calibration 214 Internal Calibration 215 Probe Calibration and De-skew 219 This chapter describes the Agilent Infiniium digital storage oscilloscope calibration procedures.
24 Calibrating the Infiniium Oscilloscope and Probe Required Equipment for Calibration To calibrate the Infiniium oscilloscope in preparation for running the DisplayPort automated tests, you need the following equipment: • Keyboard, qty = 1, (provided with the Agilent Infiniium oscilloscope). • Mouse, qty = 1, (provided with the Agilent Infiniium oscilloscope). • Precision 3.5 mm BNC to SMA male adapter, Agilent p/n 54855- 67604, qty = 2 (provided with the Agilent Infiniium oscilloscope).
Calibrating the Infiniium Oscilloscope and Probe 24 Internal Calibration This will perform an internal diagnostic and calibration cycle for the oscilloscope. For the Agilent oscilloscope, this is referred to as Calibration. This Calibration will take about 20 minutes. Perform the following steps: 1 Set up the oscilloscope with the following steps: a Connect the keyboard, mouse, and power cord to the rear of the oscilloscope.
24 Calibrating the Infiniium Oscilloscope and Probe 3 Referring to Figure 81 below, perform the following steps: a Click on the Utilities>Calibration menu to open the Calibration window. Figure 81 Accessing the Calibration Menu. 4 Referring to Figure 82 below, perform the following steps to start the calibration: a Uncheck the Cal Memory Protect checkbox. b Click the Start button to begin the calibration.
24 Calibrating the Infiniium Oscilloscope and Probe Figure 82 Oscilloscope Calibration Window 5 Follow the on- screen instructions: a You will be prompted to disconnect everything from all the inputs: click the OK button. b Then you will be prompted to connect the calibration cable with SMA adapters between the Aux Out and a specified input. Install the SMA adapter by pressing it on input BNC, and hand tightening the outer ring turning right. Click the OK button after connecting the cable as prompted.
24 Calibrating the Infiniium Oscilloscope and Probe Figure 83 Time Scale Calibration Dialog box d Click on the Std + Dflt button to continue the calibration, using the Factory default calibration factors. e When the calibration procedure is complete, you will be prompted with a Calibration Complete message window. Click the OK button to close this window. f Confirm that the Vertical and Trigger Calibration Status for all Channels passed. g Click the Close button to close the calibration window.
Calibrating the Infiniium Oscilloscope and Probe 24 Probe Calibration and De-skew Before performing DisplayPort tests you should calibrate and de- skew the probes. SMA probe head Atten/Offset Calibration 1 Referring to Figure 84 below, perform the following steps: a Ensure that a probe, attached with SMA probe head is connected to Channel 1. Install the 82 Ω resistors into the SMA probe head. Connect the de- skew fixture to Aux Out. Clip the resistors on de- skew fixture.
24 Calibrating the Infiniium Oscilloscope and Probe Figure 85 Channel Dialog Box 220 Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
Calibrating the Infiniium Oscilloscope and Probe 24 2 Referring to Figure 86 below, perform the following steps: a Click the Add Head... button, and then select E2678A:DF Sckt from the list of Head Type. Select OK to close the dialog box. Figure 86 Probe Setup Window.
24 Calibrating the Infiniium Oscilloscope and Probe 3 Referring to Figure 87 below, perform the following steps: a Click on the Calibrate Probe button to open the Probe Calibration window. Figure 87 User Defined Probe Window. 4 Referring to Figure 88 and perform the following steps: a Select the Calibrated Atten/Offset Radio Button b Click the Start Atten/Offset Calibration Button to open the Calibration window.
Calibrating the Infiniium Oscilloscope and Probe 24 Figure 88 Probe Calibration Window. c Follow the on- screen instructions. d At the end of the Atten/Offset Calibration perform the Skew Calibration. Differential Probe Head Skew Calibration This procedure ensures that the timing skew errors between channels are minimized. Perform the following steps: 1 Referring to Figure 89 below, perform the following steps: a Select the Start Skew Calibration button and follow the on- screen instructions.
24 Calibrating the Infiniium Oscilloscope and Probe manual comes together with the E2655A/B De- skew Kit, that came with your oscilloscope. Figure 89 De-skew Connection. NOTE Each probe is calibrated to the oscilloscope channel to which it is connected. Do not switch probes between channels or other oscilloscopes, or it will be necessary to calibrate them again. It is recommended that the probes are labeled with the channel on which they were calibrated.
Calibrating the Infiniium Oscilloscope and Probe 24 the Aux Out of the oscilloscope. Do not connect the negative (- ) side of the InfiniiMax probe amp to anything.
24 Calibrating the Infiniium Oscilloscope and Probe f Click on the Setup>Channel 1 menu to open the Channel Setup window. Figure 91 Channel Setup Window g Click the Probes button in the Channel Setup window, to open the Probe Setup window.
Calibrating the Infiniium Oscilloscope and Probe 24 Figure 92 Channel Dialog Box Agilent U7232A DisplayPort Electrical Performance Compliance Test Application 227
24 Calibrating the Infiniium Oscilloscope and Probe 2 Referring to Figure 93 below, perform the following steps: a Click the Add Head... button, and then select N5380A:DF SMA from the list of Head Type. Select OK to close the dialog box. Figure 93 Probe Setup Window. b Click on the Calibrate Probe button to open the Probe Calibration window.
Calibrating the Infiniium Oscilloscope and Probe 24 Figure 94 Probe Calibration Window. c Follow the on- screen instructions. d At the end of the Atten/Offset Calibration perform the Skew Calibration. SMA Probe Head Skew Calibration This procedure ensures that the timing skew errors between channels are minimized. Perform the following steps: 1 Referring to Figure 95 below, perform the following steps: a Select the Start Skew Calibration button and follow the on- screen instructions.
24 Calibrating the Infiniium Oscilloscope and Probe manual comes together with the E2655A/B De- skew Kit, that came with your oscilloscope. Figure 95 De-skew Connection.
U7232A DisplayPort Electrical Performance Compliance Test Application Method of Implementation 25 InfiniiMax Probing Figure 96 1169A InfiniiMax Probe Amplifier Agilent recommends the N5380A SMA probe head and the N5380A differential SMA probe head.
25 InfiniiMax Probing Table 30 Probe Head Characteristics 232 Probe Head Model Number Differential Measurement (BW, input C, input R) Single-Ended Measurement (BW, input C, input R) Differential socket E2678A 7 GHz, 0.34 pF, 50 kOhm 7 GHz, 0.
U7232A DisplayPort Electrical Performance Compliance Test Application Method of Implementation A DisplayPort Source Automated Test with W2642A DPTC Aux Channel and Hot Plug Detect (HPD) 234 DPTC Controller 235 Automated Test Sequence 236 This section describes the implementation of the test automation features architect in the DisplayPort Standard Version 1.1a.
A DisplayPort Source Automated Test with W2642A DPTC Aux Channel and Hot Plug Detect (HPD) DisplayPort devices communicate with each other through the aux channel. The DisplayPort sink device provides memory where a source and a sink could read/write into this memory. DisplayPort Standard 1.1a has reserved a set of DCPD registers for the purpose of test automation. There is a HPD line between a source and a sink too.
DisplayPort Source Automated Test with W2642A DPTC A DPTC Controller The Agilent W2642A DPTC can be used as a sink emulator to communicate with the source to output the desired signals. Some fundamental functions provided to enable automation are: • SetByte(Address, Value) • Send HPDPulse(Length) • PlugIn(Emulate Plug in event) • PlugOut(Emulate Plug out event) NOTE The above listed function names for informative purpose only. They do not reflect the actual API call.
A DisplayPort Source Automated Test with W2642A DPTC Automated Test Sequence This section provides information on how to enable the test automation in DisplayPort Source test. You should specify the max link rate, lane count, preEmphasis, Level and SSC option in the compliance application. OPTION 1 Step 1: Emulate successful link training (For SSC) 1 This step emulates a fake link training to cheat the source that a sink device is connected.
DisplayPort Source Automated Test with W2642A DPTC A 3 This sequences cheats the DisplayPort source that the link training has already been perform without looping through the actual link training. As such, the DisplayPort source device exits the link training successfully. 4 Aux Controller checks DOWNS_SPREAD_CTRL if SSC support has changed.
A DisplayPort Source Automated Test with W2642A DPTC Figure 101 Channel Equialization Sequence of Link Training 238 Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
A DisplayPort Source Automated Test with W2642A DPTC Step2: Change Bit Rate and Number of Lanes 1 To change the bit rate and number of lanes, DPTC controller will initiate the below sequence: a Set 0x202 (LANE0_1_STATUS) = 0x77 b Set 0x203 (LANE2_3_STATUS) = 0x77 c Set 0x204 (LANE_ALIGN__STATUS_UPDATED) = 0x81 d Set bit 0x201.1 (AUTOMATED_TEST_REQUEST) e Clear 0x218(TEST_REQUEST) f Set bit 0x218.0 (TEST_LINK_TRAINING) g Set byte 0x219 (TEST_LINK_RATE) to 0x0A(2.7 Gbps) or 0x06(1.
A DisplayPort Source Automated Test with W2642A DPTC Table 31 Mapping Table for Pre-Emphasis and Level VOLTAGE_SWING_LANEX (2 bits) 00: 400 mV 01: 600 mV 10: 800 mV 11: 1200 mV Table 32 Mapping Table for Pre-Emphasis and Level PRE-EMPHASIS_SWINT_LANEX (2 bits) 00: 0 dB 01: 3.5 dB 10: 6 dB 11: 9.5 dB f Clear 0x218 and Set bit 0x218.
A DisplayPort Source Automated Test with W2642A DPTC 2 Once a 1ms HPD pulse is received: a Source reads bit 0x201.1 (AUTOMATED_TEST_REQUEST). If 0x201.1 is asserted, go to step 2 b If 0x218.
A 242 DisplayPort Source Automated Test with W2642A DPTC Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
Index A O AC common mode noise tests, 137 overshoot tests, 69 spread spectrum clocking (ssc) tests, 111 starting the DisplayPort automated test application, 22 B P T BNC to SMA male adapter, 4, 214 precision 3.
Index 244 U7232A DisplayPort Electrical Performance Compliance Test Application
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