Technical data

126 Agilent U7232A DisplayPort Electrical Performance Compliance Test Application
14 Source Rise-Fall Mismatch Single-Ended Tests (Informative)
Test Condition
Bit Rate: all bit rates are supported.
Output Level: 800 mVolts.
Pre- Emphasis: 0 dB.
Test Pattern: PRBS 7.
SSC: If the device under test is able to operate either with SSC Enabled or
SSC Disabled then SSC Disabled will be selected. If the device is always
SSC Enabled or always SSC Disabled then the device is tested in its
normal state.
Two single- ended signals are probed independently, acquired
simultaneously and compared.
PASS Condition
Falling Mismatch ≤ 15% of the single- ended rise time
Rising Mismatch ≥ 15% of the single- ended fall time
Test Plan Check Mode Turn on test plan check mode to simulate the actual test plan run flow
without actual tests being run.
SSC Acquisitions Number of SSC cycle captured for SSC related tests. Maximum
number is 25.
Low Bit Rate SSC
Smoothing Points
Sets the number of smoothing points for SSC low pass filter when bit
rate is 1.62 Gbps.
High Bit Rate SSC
Smoothing Points
Sets the number of smoothing points for SSC low pass filter when bit
rate is 2.70 Gbps.
Memory Depth Sets the memory depth for acquisition
PRBS Validation Algorithm Settings
PRBS pattern checker
rule
Determine the rules applied to PRBS 7 Pattern detector. By selecting
Strict, test can only proceed with the correct PRBS 7 pattern only.
Expert Mode Turn on the expert mode for looser pre-requisite checker.
Single-ended Tests
Rise-Fall Mismatch
Rise-Fall Mismatch Edge Sets the number of edges measured for the rise-fall mismatch test.
Threshold Sets the threshold used to make a rise time or fall time measurement.
Table 16 Test Configuration Options
Configuration Option Description