Technical data

Source Transition Time Differential Tests (Informative) 6
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application 59
Test Condition
Bit Rate: all bit rates are supported.
Output Level: 800 mVolts.
Pre- Emphasis: 0 dB.
Test Pattern: PRBS 7.
SSC: If the device under test is able to operate either with SSC Enabled or
SSC Disabled then the device is tested for both conditions. If the device is
always SSC Enabled or always SSC Disabled then the device is tested in
its normal state.
PASS Condition
50 ps ≤ Transition Time ≤ 160 ps
Test Plan Check Mode Turn on test plan check mode to simulate the actual test plan run flow
without actual tests being run.
SSC Acquisitions Number of SSC cycle captured for SSC related tests. Maximum
number is 25.
Low Bit Rate SSC
Smoothing Points
Sets the number of smoothing points for SSC low pass filter when bit
rate is 1.62 Gbps.
High Bit Rate SSC
Smoothing Points
Sets the number of smoothing points for SSC low pass filter when bit
rate is 2.70 Gbps.
Memory Depth Sets the memory depth for acquisition
PRBS Validation Algorithm Settings
PRBS pattern checker
rule
Determine the rules applied to PRBS 7 Pattern detector. By selecting
Strict, test can only proceed with the correct PRBS 7 pattern only.
Source Differential Tests
Transit ion Time
Transition Edges Sets the number of edges measured for the transition tests.
Transition VH Pattern Sets the pattern for rise time measurement to either 01111, 0111 or
011. The default setting is 0111.
Transition VL Pattern Sets the pattern for fall time measurement to either 10000, 1000 or
100. The default setting is 1000.
Threshold Specifies the threshold in percentage.
Table 7 Test Configuration Options
Configuration Option Description