Technical data

Source Pre-Emphasis Level Differential Tests (Normative & Informative) 9
Agilent U7232A DisplayPort Electrical Performance Compliance Test Application 83
Table 11 Test Configuration Options
Configuration Option Description
Clock Recovery Settings
Clock Recovery Order Set either a second order PLL or a first order PLL method to recover the
clock.
Clock Recovery Loop
Bandwidth (D10.2) - 1.62
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2
pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (PRBS 7) -
1.62 Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when PRBS
7 pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (D10.2) - 2.7
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when D10.2
pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Loop
Bandwidth (PRBS 7) - 2.7
Gbps
Sets the 3 dB bandwidth of the loop filter used by the PLL when PRBS
7 pattern is used. Please specify in correct format; xMHz, xkHz or xHz.
Clock Recovery Damping
Factor
Sets the damping factor which is the value that used in designing the
second order PLL to recover the clock. The damping factor and the 3
dB bandwidth of the PLL are related to the natural frequency using the
following equation.
where:
Configurable Parameter Settings
Bandwidth Reduction Specifies the bandwidth frequency for the oscilloscope. This
configuration is only available when the Enhanced Bandwidth or Noise
Reduction option is installed on the oscilloscope.
ω
n
2πF
t
2ζ
2
1– 2ζ
2
1–()
2
1++
-------------------------------------------------------------------=
ω
n
the natural frequency of the PLL=
ζ the dampling factor of the PLL=
F
t
the 3 dB bandwidth of the PLL=