User`s guide

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Troubleshooting the Logic Analyzer
Inverse Assembler Problems
❏ Ensure that each analyzer pod is connected to the correct analysis probe
cable.
There is not always a one-to-one correspondence between analyzer pod
numbers and analysis probe cable numbers. Analysis probes must supply
address (ADDR), data (DATA), and status (STAT) information to the
analyzer in a predefined order, so the cable connections for each analysis
probe are often altered to support that need. Thus, one analysis probe
might require that you connect cable 2 to analyzer pod 2, while another
will require you to connect cable 5 to analyzer pod 2. See the User's Guide
for your analysis probe for further information.
❏ Check the activity indicators for status lines locked in a high or low state.
❏ Verify that the STAT, DATA, and ADDR format labels have not been
modified from their default values.
These labels must remain as they are configured by the configuration file.
Do not change the names of these labels or the bit assignments within the
labels. Some analysis probes also require other data labels; check your
Analysis Probe User's Guide for more information.
❏ Verify that all microprocessor caches and memory managers have been
disabled.
In most cases, if the microprocessor caches and memory managers remain
enabled you should still get inverse assembly, but it may be incorrect since
some of the execution trace was not visible to the logic analyzer.
❏ Verify that storage qualification has not excluded storage of all the needed
opcodes and operands.