User`s manual

110 Agilent E1330B Digital I/O Module Register Information
Appendix B
The module is a register-based slave/interrupter device, supporting VME
D16, D8(O), and D8(OE) transfers. The interrupt protocol supported is
“release on interrupt acknowledge” – an interrupt is cleared by a VXIbus
interrupt acknowledge cycle.
WARNING Registers have been documented as 8 bit bytes. If you access
them using 16 bit transfers from a Motorola CPU, the high and
low byte will be swapped. The Agilent E1300/01 Mainframe and
Agilent E1405/06 Command Modules use Motorola CPUs.
Motorola CPUs place the highest weighted byte in the lower
memory location and the lower weighted byte in the higher
memory address; Intel processors do just the opposite. VXI
registers are memory mapped, thus you will see this
Motorola/Intel byte swap difference when doing register
programming.