Technical data

Chapter 18 517
T1 Analyzer
Patterns
T1 Analyzer
Patterns
Many test patterns are available to 'stress' the circuit in a unique way or to gain
maximum insight into a particular problem. Much has been written to guide the
troubleshooter to select the proper pattern. Below is a summary of the qualities of
the patterns available in the test set.
• 1:7 - An eight-bit pattern that contains a single one. Used to test clock recovery.
• 2 in 8 - An eight bit pattern with two ones and a maximum of four consecutive
zeroes. B8ZS is never sent.
• 3 in 24 - A twenty-four bit-pattern containing 3 ones with the longest length of
consecutive zeroes constrained to fifteen. It has a ones density of 12.5% and is
used to check clock recovery.
• All 1's - A pattern that causes line drivers to consume the maximum amount of
current. If framing is set to 'Unframed' the resulting pattern is equivalent to a
'Blue Alarm' or 'Alarm Indication Signal' or AIS.
• All 0's - A pattern that is often selected to verify B8ZS provisioning.
• QRSS - A pseudorandom pattern that simulates live traffic on a circuit. It is a
very common test pattern
• T1-DALY - A pattern that changes rapidly between high and low density. This
pattern is used to stress ALBO, equalizer and timing recovery circuits.
• 55 Octet - Similar to the T1-DALY pattern except that it contains runs of fifteen
consecutive zeroes that violate ones density requirements if sent unframed.
• 2E15-1 - A pseudorandom pattern based on a 15 bit shift register.
• 2E20-1 - A pseudorandom pattern based on a 20 bit shift register.
• 2E23-1 - A pseudorandom pattern based on a 23 bit shift register.
• Alternating Ones and Zeroes - A pattern that alternates between ones and
zeroes.