User`s guide

Chapter 15 439
W-CDMA Uplink Digital Modulation for Receiver Test
W-CDMA Uplink Concepts
Signal Descriptions for W-CDMA Uplink
Figure 15-60 shows how W-CDMA uplink input and output signals align with respect to time.
Notice that all signals are aligned with the leading edge of the chip clock pulse.
Figure 15-60 Input/Output Signal Alignment
DPCH Mode
Table 15-7 provides descriptions for fixed and user-selectable signals available in DPCH
mode. Figure 15-61 on page 441 shows an example of DPCH output timing alignment.
Table 15-7 Signal Descriptions for DPCH Mode
Signal Label Input/
Output
Signal Description SCPI
Syntax
Frame Sync Trigger Input The input signal can be set to either the
frame clock or the system frame number
SFN) reset signal by toggling the
Sync Source
FClk SFN
softkey. The frame clock can be set
to 10, 20, 40, 80, or 2560 ms.
FSYN
TPC User File
Trigger
Input Trigger for user-defined TPC bits. USER