Specifications

4-28 Fully Coded 3GPP W-CDMA Personality User’s and Programming Guide
Operation ESG Family Signal Generators
Understanding the Uplink Configuration Option 200
Reference Measurement Channels
Option 200 provides reference measurement channels at 12.2, 64, 144, and 384 kbits per
second. This option also provides transport layer channelization for AMR 12.2 (adaptive
multi-rate) and UDI 64 (unrestricted digital information) protocols.
System Triggering and Synchronization
Either of the system frame number reset signal or the frame clock which is applied to the
PATTERN TRIG IN port can be set as a system trigger signal. After a delay time defined
by the sum of 1024 chips (T0 = the standard timing offset between downlink and uplink),
Timing Offset, and Slot Delay (plus 10 ms when the SFN reset signal is used), a sync
signal is generated to time align all other signals. The RF output signal is generated after
the fixed delay of the processing time by the hardware.
For increased measurement accuracy, the signal generator’s rear panel 10 MHZ OUT
frequency reference can be utilized by other instruments in the test system.
Uplink I/O Signal Descriptions and Timing Relationships
The following sections describe the functionality and timing relationships of various input
and output signals available at the BNC connectors on the Option 200 signal generator.
Option 200 changes some of the standard characteristics of these signals for use with
3GPP applications.
Front Panel BNC Input Connectors
Other input connectors are used for configuring the downlink tests.
DATA CLOCK This BNC connector is used for chip clock input.
For use with external data clock sources. To use an external signal source as the data clock
input, press
BBG Data Clock Ext Int until Ext is highlighted or execute the appropriate SCPI
command. This clock rate can be multiplied by setting the
Ext Clock Rate softkey to x2 or
x4. Also, the polarity of this signal can be selected by the
Ext Clock Polarity softkey to either
Pos (positive) or Neg (negative).
Rear Panel BNC Input/Output Connectors
PATTERN TRIG IN This BNC connector is used for system reset trigger input.
The input signal can be set to either the frame clock or the system frame number reset
signal by toggling the
Sync Source FClk SFN softkey. The frame clock is selectable from 10,
20, 40, and 80 ms.
EVENT 1 OUT This BNC connector is used for raw data output of the DPDCH channel.
The DPDCH raw data is aligned with the clock signal (EVENT 2) for the DPDCH raw
data. The length of this raw data is dependent on the slot format currently selected for the
DPDCH channel.