Specifications

Fully Coded 3GPP W-CDMA Personality User’s and Programming Guide 4-29
ESG Family Signal Generators Operation
Option 200 Understanding the Uplink Configuration
EVENT 2 OUT This BNC connector is used for clock signal output for DPDCH raw data.
This clock signal is aligned with the DPDCH raw data. The one-cycle length is dependent
on the slot format currently set to the DPDCH channel.
DATA OUT This BNC connector is used for DPCCH raw data output.
The value aligned with the 15 ksps symbol rate may change every 256 chips. The output is
aligned with data generation timing and leads the RF output by typically 33 chips.
SYMBOL SYNC OUT This BNC connector is used for system sync output.
The sync output signal is triggered by the system frame number reset signal or by the
frame clock which is applied to the PATTERN TRIG IN connector. With this sync signal,
the time alignment of the earliest frame timing for baseband data generation is made. A
number of frames are generated until the next sync signal is introduced for time
alignment. The delay time from the trigger input is the sum of 1024 chips (T0), Timing
Offset, and Slot Delay (also add 10 ms if the SFN reset signal is used).
This output can be used to synchronize receiver measurements of the base station.
Uplink I/O Signal Timing Diagram
The following figure illustrates the timing relationships between the signals from the rear
panel BNC input and output connectors. Signal states are referenced to the chip clock
provided at the DATA CLK OUT connector.