Specifications

Programming Guide 1-45
ESG Family Signal Generators Preparing for Use
Programming the Status Register System
The Status Byte Group consists of the Status Byte Register and the Service Request
Enable Register. The Status Byte Register contains the following bits:
Figure 1-18.
Bit Description
0, 1 These bits are always set to 0.
2 A 1 in this bit position indicates that the SCPI error queue is not empty. The SCPI error
queue contains at least one error message.
3 A 1 in this bit position indicates that the Data Questionable summary bit has been set.
The Data Questionable Event Register can then be read to determine the specific
condition that caused this bit to be set.
4 A 1 in this bit position indicates that the signal generator has data ready in the output
queue. There are no lower status groups that provide input to this bit.
5 A 1 in this bit position indicates that the Standard Event summary bit has been set. The
Standard Event Status Register can then be read to determine the specific event that
caused this bit to be set.
6 A 1 in this bit position indicates that the instrument has at least one reason to require
service. This bit is also called the Master Summary Status bit (MSS). The individual bits
in the Status Byte are individually ANDed with their corresponding service request
enable register, then each individual bit value is ORed and input to this bit.
7 A 1 in this bit position indicates that the Standard Operation summary bit has been set.
The Standard Operation Event Register can then be read to determine the specific
condition that caused this bit to be set.