Specifications

Programming Guide 1-55
ESG Family Signal Generators Preparing for Use
Programming the Status Register System
The Data Questionable Status Group is used to determine the specific event that set bit 3
in the Status Byte Register. The Data Questionable Status Group consists of the Data
Questionable Condition Register, the Data Questionable Negative Transition Filter, the
Data Questionable Positive Transition Filter, the Data Questionable Event Register, and
the Data Questionable Event Enable Register. The Data Questionable Condition Register
contains the following bits:
Figure 1-27.
Bit Description
0, 1, 2 Unused. These bits are always set to 0.
3 This is a summary bit taken from the QUEStionable:POWer register. A 1 in this bit
position indicates that one of the following may have happened: The ALC (Automatic
Leveling Control) is unable to maintain a leveled RF output power (i.e., ALC is
UNLEVELED), or the reverse power protection circuit has been tripped.
4 A 1 in this bit position indicates that the internal reference oscillator (reference oven)
is cold.
5 This is a summary bit taken from the QUEStionable:FREQuency register. A 1 in this
bit position indicates that one of the following may have happened: synthesizer PPL
unlocked, 10 MHz reference VCO PPL unlocked, heterodyned VCO PPL unlocked, or
baseband PPL unlocked. See the Data Questionable Frequency Status Group for more
information.
6 Unused. This bit is always set to 0.
7 This is a summary bit taken from the QUEStionable:MODulation register. A 1 in this
bit position indicates that one of the following may have happened: modulation source
1 underrange, modulation source 1 overrange, modulation source 2 underrange, or
modulation source 2 overrange. See the Data Questionable Modulation Status Group
for more information.