Specifications

1-56 Programming Guide
Preparing for Use ESG Family Signal Generators
Programming the Status Register System
The Data Questionable Condition Register continuously monitors the hardware and
firmware status of the instrument. Condition registers are read-only. To query the
condition register, send the command STATus:QUEStionable:CONDition? The response
will be the decimal sum of the bits which are set to 1. For example, if bit number 9 and bit
number 3 are set to 1, the decimal sum of the 2 bits is 512 plus 8. So the decimal value 520
is returned.
The transition filter specifies which types of bit state changes in the condition register will
set corresponding bits in the event register. The changes may be positive (from 0 to 1) or
negative (from 1 to 0). Send the command STATus:QUEStionable:NTRansition <num>
(negative) or STATus:QUEStionable:PTRansition <num> (positive) where <num> is the
sum of the decimal values of the bits you want to enable.
The Data Questionable Event Register latches transition events from the condition
register as specified by the transition filters. Event registers are destructive read-only.
Reading data from an event register will clear the content of that register. To query the
event register, send the command STATus:QUEStionable[:EVENt]?
8 This is a summary bit taken from the QUEStionable:CALibration register. A 1 in this
bit position indicates that one of the following may have happened: an error has
occurred in the DCFM/DC
ΦM zero calibration or an error has occurred in the I/Q
calibration. See the Data Questionable Calibration Status Group for more
information.
9 A 1 in this bit position indicates that a self-test has failed during power-up. This bit
can only be cleared by cycling the instrument’s line power. *CLS will not clear this bit.
10, 11 Unused. These bits are always set to 0.
12 This is a summary bit taken from the QUEStionable:BERT register. A 1 in this bit
position indicates that one of the following may have happened: no clock, no data
change, or sync loss state for a bit error rate test (Option UN7 only). See the Data
Questionable Calibration Status Group for more information.
13, 14 Unused. These bits are always set to 0.
15 Always Zero (0).
Bit Description