Specifications

1-62 Programming Guide
Preparing for Use ESG Family Signal Generators
Programming the Status Register System
Figure 1-33.
The Data Questionable Frequency Condition Register continuously monitors output
frequency status of the instrument. Condition registers are read-only. To query the
condition register, send the command STATus:QUEStionable:FREQuency:CONDition?
The response will be the decimal sum of the bits which are set to 1.
The transition filter specifies which types of bit state changes in the condition register will
set corresponding bits in the event register. The changes may be positive (from 0 to 1) or
negative (from 1 to 0). Send the command
STATus:QUEStionable:FREQuency:NTRansition <num> (negative) or
STATus:QUEStionable:FREQuency:PTRansition <num> (positive) where <num> is the
sum of the decimal values of the bits you want to enable.
Bit Description
0 A 1 in this bit indicates that the synthesizer is unlocked.
1 A 1 in this bit indicates that the 10 MHz reference signal is unlocked.
2 A 1 in this bit indicates that the 1 GHz reference signal is unlocked.
3 A 1 in this bit indicates that the baseband data clock synthesizer is unlocked.
4 A 1 in this bit indicates that the ARB is unlocked.
5 A 1 in this bit indicates that the sampler loop is unlocked.
6 A 1 in this bit indicates that the YO loop is unlocked.
7
−14 Unused. These bits are always set to 0.
15 Always Zero (0).