Specifications

11
The physical hardware configuration for the two-box setup is shown in
Figure 7. Two ESG signal generators, each with options UN8 and 201, are
required. ESG #1 is used to generate the Pilot, Sync, OCNS, and Paging
channels. ESG #2 provides the Traffic channels and the 1.2288 MHz chip
clock that drives the data clock for both ESGs with matched delays; the
Data Clock input clips the RF to TTL levels (refer to the note regarding
cable lengths in Figure 7.)
The I and Q outputs for the channel data are summed together with
T-connectors; splitters/combiners are not required since mismatch is not
significant. Each ESG’s I/Q power levels are independent of each other;
refer to the section titled Power Mapping Procedure for more information
on this.
System synchronization between ESG #1 and ESG #2 uses two external
connections. In the first connection, EVENT 2 of ESG #1 provides a
system reset to the ESG #2 PATTERN TRIG IN. Any change in the state of
ESG #1 requiring a reset of long code and channel frame timing will gener-
ate a system reset and re-sync both ESG's. For the second connection,
the even second output from ESG #2’s SYMBOL SYNC OUT is connected
to ESG #1’s BURST GATE IN. If ESG #1 detects a misalignment of the
even second output from ESG #2 with its internal even second clock,
then a system sync output will be generated by ESG #1 to re-synchronize
both ESGs. Additionally, as with the one-box setup, EVENT 1 provides a
variable Delayed Even Second clock for synchronizing other equipment.
Note: Matched short cable lengths (i.e. L1 = L1; L2 = L2; L3 = L3) are important to reduce phase difference. L4 should
also be kept very short.
Similar to the example for the one-box setup, on page 12, an example is
provided for a two-box setup. This example provides a Pilot, Synch, OCNS,
and Paging channel, as well as a Fundamental RC4 traffic channel, and a
Supplemental RC4 traffic channel.
Figure 7. Two-box configuration for mobile receiver test
T
ESG #1
Q OUT
I OUT
Q OUT I OUT
Q INPUT
I INPUT
DATA CLOCK
DATA CLOCK
Rear Panel
Rear Panel
Symbol Sync OUT Pattern Trig IN
EVENT 2 10 MHz OUT
Q INPUT
I INPUT
RF OUTPUT
RF OUTPUT
(chip clock)
10 MHz IN
Burst Gate IN
EVENT 1
Delayed
Even Second
(To DUT)
ESG #2
T
T
L3
L3
L1
L1
L4
L2
L2
L2
L2