Specifications

Loop Suppression: This indicates whether or not the Phase Lock Loop
(PLL) Suppression was verified. The PLL Suppression verification verifies
the accuracy of the Phase Detector Constant and VCO Tuning Constant.
For all PLL measurements, the system generates a Theoretical Loop
Suppression correction and applies it to the measured noise data. When
Verification of the Loop Suppression is specified, the system measures
the suppression of the phase lock loop and compares the measured
suppression to the Theoretical suppression. By adjusting the PTR and the
Assumed Pole, the Theoretical suppression is fit to the measured Loop
Suppression. If a significant modification is required, the system notifies
you of an Accuracy Specification Degradation.
Acc'y Spec Degrad: This parameter only appears when Verification of the
Loop Suppression is selected, and the Theoretical Loop Suppression must
be modified beyond acceptable limits to match it to the measured loop
suppression. If the indicated Accuracy Specification Degradation is greater
than zero, the VCO Tuning Constant or the Phase Detector Constant is in
error at an offset frequency near the PLL BW, or some other problem is
effecting the PLL BW, such as injection locking.
Without specific information about the source of the problem, it should be
assumed that the accuracy specification for the Results Graph at all offsets
has been degraded by the Accuracy Specification Degradation value. That
is to say, the specified accuracy of the HP 3048A becomes ±2 dB + the
Accuracy Specification Degradation for frequencies of 0.001 Hz to 1 MHz,
and ±4 dB + Accuracy Specification Degradation for frequencies from
greater than 1 MHz to 40 MHz. To minimize an Accuracy Specification
Degradation, identify and eliminate the probable cause, then initiate a
New Measurement with Loop Suppression Verification selected.
Param Summary 3-9