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Agilent Technologies 16750A/B Logic Analyzer The Agilent Technologies 16750A/B 400 MHz State/2 GHz Timing Zoom logic analyzer offers 4M deep memory and very fast sample rates - up to 2 GHz for areas around the trigger - with up to 340 channels. “Getting Started” on page 11 “Task Guide” on page 31 • “Step 1. Connect the logic analyzer to the device under test” on page 13 • “Step 2. Choose the sampling mode” on page 14 • “Step 3. Format labels for the probed signals” on page 17 • “Step 4.
Agilent Technologies 16750A/B Logic Analyzer • “Reference” on page 113 “Concepts” on page 191 See Also “Running Measurements” on page 86 • “Displaying Captured Data” on page 88 • “Using Symbols” on page 95 • “Printing/Exporting Captured Data” on page 104 • “Solving Logic Analysis Problems” on page 108 • “Saving and Loading Logic Analyzer Configurations” on page 110 • “The Sampling Tab” on page 115 • “The Format Tab” on page 119 • “The Trigger Tab” on page 146 • “The Symbols Tab” on pag
Agilent Technologies 16750A/B Logic Analyzer 4
Contents Agilent Technologies 16750A/B Logic Analyzer 1 Getting Started Step 1. Connect the logic analyzer to the device under test Step 2. Choose the sampling mode 14 Step 3. Format labels for the probed signals Step 4. Define the trigger condition Step 5. Run the measurement 17 20 21 Step 6. Display the captured data For More Information...
Contents To select transitional timing or store qualified 37 More on Store Qualification in Transitional Timing 38 More on Storing Transitions 38 Transitional Timing Considerations 39 Selecting the State Mode (Synchronous Sampling) 43 In Either Timing Mode or State Mode 52 Using 2 GHz Timing Zoom 54 Formatting Labels for Logic Analyzer Probes 57 To assign pods to one or two analyzers 57 To set pod threshold voltages 58 To assign probe channels to labels 59 To change the label polarity 61 To reorder bi
Contents Using Symbols 95 To load object file symbols 96 To adjust symbol values for relocated code To create user-defined symbols 98 To enter symbolic label values 99 To create an ASCII symbol file 100 To create a readers.
Contents Importing Netlist and ASCII Files 121 Exporting ASCII Files 123 Importing ASCII Files 123 Termination Adapter 125 E5346A High Density Adapter 126 Mapping Connector Names 127 Import the Net List File 127 Verify Net to Label Mapping 128 Select/Create Interface Labels 129 Pod Assignment Dialog 130 Sampling Positions Dialog 131 The Trigger Tab 146 Trigger Functions Subtab 147 Settings Subtab 154 Overview Subtab 155 Default Storing Subtab 156 Status Subtab 157 Save/Recall Subtab 157 The Symbols T
Contents Error Messages 170 Must assign Pod 1 on the master card to specify actions for flags 171 Branch expression is too complex 171 Cannot specify range on label with clock bits that span pod pairs 176 Counter value checked as an event, but no increment action specified 177 Goto action specifies an undefined level 177 Maximum of 32 Channels Per Label 177 Hardware Initialization Failed 178 Must assign another pod pair to specify actions for flags 178 No more Edge/Glitch resources available for this pod
Contents 4 Concepts Understanding Logic Analyzer Triggering The Conveyor Belt Analogy 192 Summary of Triggering Capabilities 194 Sequence Levels 194 Boolean Expressions 197 Branches 198 Edges 198 Ranges 198 Flags 199 Occurrence Counters and Global Counters Timers 200 Storage Qualification 201 Strategies for Setting Up Triggers 203 Conclusions 207 192 199 Understanding State Mode Sampling Positions Glossary Index 10 208
1 Getting Started After you have connected the logic analyzer probes to your device under test (see “Step 1.
Chapter 1: Getting Started • “Step 2. Choose the sampling mode” on page 14 • “Step 3. Format labels for the probed signals” on page 17 • “Step 4. Define the trigger condition” on page 20 • “Step 5. Run the measurement” on page 21 • “Step 6.
Chapter 1: Getting Started Step 1. Connect the logic analyzer to the device under test Step 1. Connect the logic analyzer to the device under test Before you begin setting up the logic analyzer for a measurement, you need to physically connect the logic analyzer to your device under test. There are several ways to connect logic analyzer probes to the device under test: • Using the general-purpose probes, the standard flying lead set, and grabbers to connect to pins and leads in the device under test.
Chapter 1: Getting Started Step 2. Choose the sampling mode Step 2. Choose the sampling mode There are two logic analyzer sampling modes to choose from: timing mode and state mode. In timing mode, the logic analyzer samples asynchronously, based on an internal sampling clock signal. In state mode, the logic analyzer samples synchronously, based on a sampling clock signal (or signals) from the device under test.
Chapter 1: Getting Started Step 2. Choose the sampling mode If you chose Timing Mode 1. Select the timing analyzer full/half channel configuration. Typically, you can choose a half-channel configuration with faster sampling and greater memory depth, but with half of the channels. 2. Set the sample period. To capture signal level changes reliably, the sample period should be less than half (many engineers prefer one-fourth) of the period of the fastest signal you want to measure.
Chapter 1: Getting Started Step 2. Choose the sampling mode You can also specify clock input signal levels (from the device under test) that will enable (qualify) the sampling clock. In either sampling mode 1. Specify the trigger position. The trigger is the event in the device under test that you want to capture data around.
Chapter 1: Getting Started Step 3. Format labels for the probed signals Step 3. Format labels for the probed signals When a logic analyzer probes hundreds of signals in a device under test, you need to be able to give those channels more meaningful names than "pod 1, channel 1". The Format tab is mainly for assigning bus and signal names (from the device under test), to logic analyzer channels. These names are called labels. Labels are used when setting up triggers and displaying captured data.
Chapter 1: Getting Started Step 3. Format labels for the probed signals To assign pods to one or two logic analyzers A logic analyzer's pod pairs can be assigned to one or two separate logic analyzers or they can be left unassigned. 1. In the Format tab, select the Pod Assignment button. 2. In the Pod Assignment dialog, drag a pod pair to the appropriate logic analyzer. 3. Select the Close button.
Chapter 1: Getting Started Step 3. Format labels for the probed signals To assign names to logic analyzer channels 1. Select a label button, and either: • Choose the Rename command, enter the label name, and select the OK button. • Or, choose the Insert before or Insert after command, enter the label name, and select the OK button. 2. In the label row, select the button of the pod that contains the channels you want to assign. 3. Either choose one of the standard label assignments--dots (.
Chapter 1: Getting Started Step 4. Define the trigger condition Step 4. Define the trigger condition The trigger is the event in the device under test that you want to capture data around. 1. In the Trigger tab, and in the Trigger Functions subtab, choose the type of trigger you want to specify, and select the Replace button. 2. In the Trigger Sequence portion of the Trigger tab, select the buttons to define the label values and/or other conditions you want to trigger on. Next: “Step 5.
Chapter 1: Getting Started Step 5. Run the measurement Step 5. Run the measurement Once the trigger condition has been defined, you can run the measurement. 1. Select the Run Single button . When you run a measurement, the Stop button becomes available while the logic analyzer looks for the trigger condition.
Chapter 1: Getting Started Step 6. Display the captured data Step 6. Display the captured data Once you have run a measurement and filled the logic analyzer's acquisition memory with captured data, you can display it with one of the display tools. To open Waveform or Listing displays Waveform displays are typically used when data is captured with the timing sampling mode, and Listing displays are used when data is captured with the state sampling mode. 1.
Chapter 1: Getting Started Step 6. Display the captured data 3. Drag the display tool icon and drop it on the analyzer icon. 4. To open the display tool, select its icon and choose the Display command. Next: “For More Information...
Chapter 1: Getting Started For More Information... For More Information... On making • measurements on the demo counter board: • “Example: Timing measurement on counter board” on page 26 “Example: State measurement on counter board” on page 28 • Making Basic Measurements for a self-paced tutorial • “Probing the Device Under Test” on page 33 • Setup Assistant (see the Setup Assistant help volume) (when using analysis probes).
Chapter 1: Getting Started For More Information...
Chapter 1: Getting Started Example: Timing measurement on counter board Example: Timing measurement on counter board This example uses the demo counter board that is supplied with the Making Basic Measurements kit as the device under test. The kit is supplied with every logic analysis system, or can be ordered from your Agilent Technologies Sales Office. To connect the logic analyzer to the device under test 1. Connect Pod 1 of the logic analyzer to J1 on the demo counter board.
Chapter 1: Getting Started Example: Timing measurement on counter board To run the measurement 1. Select the Run Single button. To display the captured data 1. From the Window menu, select your logic analyzer and choose the Waveform command. See Also “For More Information...
Chapter 1: Getting Started Example: State measurement on counter board Example: State measurement on counter board This example uses the demo counter board that is supplied with the Making Basic Measurements kit as the device under test. The kit is supplied with every logic analysis system, or can be ordered from your Agilent Technologies Sales Office. To connect the logic analyzer to the device under test 1. Connect Pod 1 of the logic analyzer to J1 on the demo counter board.
Chapter 1: Getting Started Example: State measurement on counter board To run the measurement 1. Select the Run Single button. To display the captured data 1. From the Window menu, select your logic analyzer and choose the Listing command. See Also “For More Information...
Chapter 1: Getting Started Example: State measurement on counter board 30
2 Task Guide • “Probing the Device Under Test” on page 33 • “Choosing the Sampling Mode” on page 36 • “Selecting the Timing Mode (Asynchronous Sampling)” on page 36 31
Chapter 2: Task Guide • “Selecting the State Mode (Synchronous Sampling)” on page 43 • “In Either Timing Mode or State Mode” on page 52 • “Using 2 GHz Timing Zoom” on page 54 • “Formatting Labels for Logic Analyzer Probes” on page 57 • “Setting Up Triggers and Running Measurements” on page 64 • “Using Trigger Functions” on page 65 • “Using State Mode Trigger Features” on page 70 • “Editing the Trigger Sequence” on page 72 • “Editing Advanced Trigger Functions” on page 78 • “Saving/Recalli
Chapter 2: Task Guide Probing the Device Under Test Probing the Device Under Test The figures below shows a variety of simple probing connections. The specific probe type, number of probes, and location on the device under test circuit depends on your particular measurement. For equivalent circuit diagrams and pinouts, see the description of the probe type in the Logic Analysis System and Measurement Modules Installation Guide.
Chapter 2: Task Guide Probing the Device Under Test Adapter-to-Board Connection Both the 01650-63203 and the E5346A adapters include termination for the logic analyzer. The 01650-63203 termination adapter plugs into a 2 x 10 pin header with 0.1 inch spacing. The E5346A high-density adapter connects to an AMP "Mictor 38" connector. If possible, use support shrouds around the Mictor connector to relieve strain and improve connections.
Chapter 2: Task Guide Probing the Device Under Test correctly, and may include an inverse assembler. The circuit board provides access to logical groups of pins through headers designed to connect directly to the logic analyzer. The easiest way to set up a measurement with an analysis probe is the Setup Assistant (see the Setup Assistant help volume). The Setup Assistant asks you questions about your measurement and then shows you just the information you need to set up the probe correctly.
Chapter 2: Task Guide Choosing the Sampling Mode Choosing the Sampling Mode There are two logic analyzer sampling modes to choose from: timing mode and state mode. In timing mode, the logic analyzer samples asynchronously, based on an internal sampling clock signal. In state mode, the logic analyzer samples synchronously, based on a sampling clock signal (or signals) from the device under test. Typically, the signal used for sampling in state mode is a state machine or microprocessor clock signal.
Chapter 2: Task Guide To select transitional timing or store qualified To select transitional timing or store qualified 1. In the Sampling tab with Timing Mode selected, select the Transitional Timing with Store Qualification configuration. Transitional Timing In Conventional Timing Acquisition mode, the analyzer stores measurement data at each sampling interval.
Chapter 2: Task Guide To select transitional timing or store qualified More on Store Qualification in Transitional Timing When Transitions is selected on the Default Storing subtab, the default store qualification is setup to store data on all channels if an edge/transition occurs on any one channel. Only active channels (channels assigned to labels) are used. No further user action is required.
Chapter 2: Task Guide To select transitional timing or store qualified happen at this rate, two samples are stored (four at the fastest rate of 2.5 ns) for every transition. Therefore, with 2 K samples of memory, 1 K of transitions are stored. You must subtract one, which is necessary for a starting point, for a minimum of 1023 stored transitions.
Chapter 2: Task Guide To select transitional timing or store qualified Sequence level branching In transitional timing, only 2 branches are available per sequence level. Global counters In transitional timing, only one global counter is available. Storing Time Tags Transitional timing requires time tags to recreate the data. Time tags are either stored in the memory resources of an unused pod pair, or they are interleaved with the data in memory.
Chapter 2: Task Guide To select transitional timing or store qualified 2. Select the Sampling tab. 3. Choose the Timing Mode option. You can also select the timing sampling mode in the “Pod Assignment Dialog” on page 130. To select the full/half channel configuration 1. In the Sampling tab, with Timing Mode selected, select the timing analyzer configuration.
Chapter 2: Task Guide To select transitional timing or store qualified NOTE: When the Sample Period is 1.25 ns, data is acquired at four times the trigger sequencer rate. This, along with other half-channel mode characteristics, means that data must be present for at least five samples before the trigger sequencer can reliably detect it. The trigger sequencer cannot detect data present for less than two sample periods, and could miss data present for less than five sample periods.
Chapter 2: Task Guide To select transitional timing or store qualified Selecting the State Mode (Synchronous Sampling) In state mode, the logic analyzer samples synchronously, based on a sampling clock signal (or signals) from the device under test. Typically, the signal used for sampling in state mode is a state machine or microprocessor clock signal.
Chapter 2: Task Guide To select transitional timing or store qualified To select the state mode 1. Open the logic analyzer Setup window. 2. Select the Sampling tab. 3. Choose the State Mode option. You can also select the state sampling mode in the “Pod Assignment Dialog” on page 130. To select the 200 MHz/400 MHz state speed configuration 1. In the Sampling tab, with State Mode selected, select the state analyzer configuration.
Chapter 2: Task Guide To select transitional timing or store qualified saved into one sample of logic analyzer memory. Two additional sampling clock modes let you capture data differently: • In the Master/Slave mode, you can save data captured on different clock edges into the same sample of logic analyzer memory. When the slave clock occurs, data captured on the pods that use the slave clock is saved in a slave latch.
Chapter 2: Task Guide To select transitional timing or store qualified To set up the master/slave sampling clock mode 1. In the Sampling tab, with State Mode selected, select the Master/Slave mode in the Clock Setup area. 2. In the Format tab, select Slave Clock for each pod that should use the slave clock, and select Master Clk for each pod that should use the master clock. To set up the demultiplex sampling clock mode 1.
Chapter 2: Task Guide To select transitional timing or store qualified See Also “To change the sampling clock mode” on page 44 To automatically adjust sampling positions When adjusting the state mode sampling position with eye finder, the logic analyzer looks at signals from the device under test, figures out the location of the data valid window in relation to the sampling clock, and automatically sets the sampling position.
Chapter 2: Task Guide To select transitional timing or store qualified The Use demo data (no probes required) option is for demonstration purposes only. 8. Choose the labels that you wish to run eye finder on. You may want to run eye finder on channel subsets, for example, when certain bus signals transition in one operating mode (of the device under test) and other bus signals transition in a different operating mode. 9. Select the Run Eye Finder button.
Chapter 2: Task Guide To select transitional timing or store qualified To view eye finder data as a bus composite When you want a compressed, high-level view of the eye finder data: 1. In the Eye Finder Results tab, select the label button and choose the View as Bus Composite command. Average sampling positions as well as stable and transitioning areas are displayed for the whole label. This is the default. Stable areas show positions where every channel in the label is stable.
Chapter 2: Task Guide To select transitional timing or store qualified 2. In the file browser dialog, name the file to be saved or select the file to be loaded. For more information on save/load messages, see “Eye Finder Load/Save Messages” on page 141.
Chapter 2: Task Guide To select transitional timing or store qualified setup time is the front edge of the setup/hold window relative to the sampling clock, and the hold time is the back edge of the setup/hold window relative to the sampling clock. 1. Select the state (synchronous sampling) mode (see “To select the state mode” on page 44). 2. In the Format tab, select the Setup/Hold button. 3. In the Sampling Positions dialog, select the Manual Setup/Hold option. 4. For each label, enter setup/hold values.
Chapter 2: Task Guide To select transitional timing or store qualified (The actual sampling position is in the middle of the setup/hold window.
Chapter 2: Task Guide To select transitional timing or store qualified not look for a trigger until the specified percentage of pretrigger data has been stored. After a trigger has been detected, the specified percentage of posttrigger data is stored before the analyzer halts. In State and Transitional Store Qualified modes, when a Run is started, the analyzer immediately looks for the trigger condition.
Chapter 2: Task Guide To select transitional timing or store qualified 2. In the Analyzer Shutdown Options dialog, choose either: • Soft -- This will leave the logic analyzer window but turn off most options. • Hard -- This will remove the logic analyzer and its display tools from the Workspace. You can also turn an analyzer off in the “Pod Assignment Dialog” on page 130. To turn an analyzer back on 1.
Chapter 2: Task Guide To select transitional timing or store qualified 1. In the Sampling tab, select the Timing Zoom button. 2. In the Timing Zoom controls dialog, select the On/Off checkbox. To set the Timing Zoom trigger position 1. In the Sampling tab, select the Timing Zoom button. 2. In the Timing Zoom controls dialog, select the trigger position.
Chapter 2: Task Guide To select transitional timing or store qualified To specify which analyzer has Timing Zoom NOTE: If you have both analyzers of the module turned on, you need to specify which analyzer you want to use Timing Zoom with. 1. In the Sampling tab, select the Timing Zoom button. 2. In the Timing Zoom controls dialog, select the analyzer that Timing Zoom will work with.
Chapter 2: Task Guide Formatting Labels for Logic Analyzer Probes Formatting Labels for Logic Analyzer Probes The Format tab is mainly for assigning bus and signal names (from the device under test) to logic analyzer channels. These names are called labels. Labels are used when setting up triggers and displaying captured data.
Chapter 2: Task Guide Formatting Labels for Logic Analyzer Probes When using a multi-card logic analyzer: • When both analyzers are turned on, pods 1/2 and 3/4 of the master card cannot be assigned to the same analyzer. • Each pod pair has two clock channels, but only the clock channels of pods on the master card can be used in the analyzer's clocking setup. (The master card's pods needn't be assigned in order to use their clock channels). To turn on an analyzer that is off 1.
Chapter 2: Task Guide Formatting Labels for Logic Analyzer Probes • LVCMOS 1.5v -- The threshold level is +0.75 volts. • LVCMOS 1.8v -- The threshold level is +0.90 volts. • LVCMOS 2.5v -- The threshold level is +1.25 volts. • LVCMOS 3.3v -- The threshold level is +1.65 volts. • CMOS 5.0v -- The threshold level is +2.50 volts. • ECL -- The threshold level is -1.3 volts. • LVPECL -- The threshold level is 2.00 volts. 3.
Chapter 2: Task Guide Formatting Labels for Logic Analyzer Probes • Or, choose the Insert before or Insert after command, enter the label name, and select the OK button. 2. In the label row, select the button of the pod that contains the channels you want to assign. 3. Either choose one of the standard label assignments or choose Individual. ( * ) (asterisk) indicates an assigned bit. ( . ) (period) indicates an unassigned bit. ( R ) indicates an assigned bit in a reordered label.
Chapter 2: Task Guide Formatting Labels for Logic Analyzer Probes “To turn labels off or on” on page 62 “To change the label polarity” on page 61 To change the label polarity While negative logic is rare in circuits (the main exception at this time is RAMBUS), you can change the label polarity if the device under test uses negative logic. 1. In the Format tab, select the polarity button (next to the label button) to toggle between positive (+) and negative (-) polarity.
Chapter 2: Task Guide Formatting Labels for Logic Analyzer Probes 3. In the Change Bit Order dialog: • To reorder the bits individually, enter the bit that the probe channel should be mapped to. • To swap the high and low order bytes or words, select the button Big Endian to Little Endian at the bottom of the dialog. • To return to sequentially ordered bits, select the button Default Order at the bottom of the dialog. 4. Select the OK button.
Chapter 2: Task Guide Formatting Labels for Logic Analyzer Probes The label's data appears in the display windows.
Chapter 2: Task Guide Setting Up Triggers and Running Measurements Setting Up Triggers and Running Measurements The following information is a generic discussion about triggering in logic analyzers. Depending on the logic analyzer type, and the state or timing mode being used, some functionality may not be available. In General...
Chapter 2: Task Guide Setting Up Triggers and Running Measurements sequence levels, the question about what to do with the captured data samples. Of course, sometimes it's useful to specify storage qualifiers at certain levels in the trigger sequence. For this, you can insert storage actions in the trigger sequence before trigger or goto actions. Storage actions in the trigger sequence override the default storage qualifier for the samples that cause the trigger or goto actions to occur.
Chapter 2: Task Guide Setting Up Triggers and Running Measurements and options. To specify a label pattern event Label pattern events let you specify patterns or ranges on a bus. 1. Select the label name button and choose the label that you want to look for a pattern on. You can also insert other label events if you want to look for multiple patterns on multiple labels.
Chapter 2: Task Guide Setting Up Triggers and Running Measurements edge events are only available in certain timing mode trigger functions. 1. Select the label name button and choose the label that you want to look for a pattern on. You can also insert other label events if you want to look for multiple patterns on multiple labels. Once another label event is inserted, you can choose And if both label events must occur in the same sample or Or if only one of the label events must occur. 2.
Chapter 2: Task Guide Setting Up Triggers and Running Measurements To expand a trigger function 1. In the Trigger tab, select the number button of the trigger sequence level whose trigger function you want to expand. 2. Choose Expand function. To compress a trigger function Expanded trigger functions can be compressed back into their original form. 1. In the Trigger tab, select the number button of the trigger sequence level whose trigger function you want to compress. 2. Choose Compress function.
Chapter 2: Task Guide Setting Up Triggers and Running Measurements NOTE: • Insert and break down trigger functions from the loaded library just like normal trigger functions. • Copy trigger function libraries to other logic analysis systems and load them into other logic analyzers that have trigger function library capability. • Edit the trigger function library, adding or deleting functions, or delete the library.
Chapter 2: Task Guide Setting Up Triggers and Running Measurements Using State Mode Trigger Features When the logic analyzer sampling mode is state, you can specify whether a state or time count is stored with samples and you can set up the default storing options.
Chapter 2: Task Guide Setting Up Triggers and Running Measurements To Specify Default Storing You can set up default storing so that only the data samples you're interested in are saved in logic analyzer acquisition memory. NOTE: Default storing in both state and timing modes require time tags to reconstruct the data. These time tags will be stored either in the memory resources of an unused pod pair, or interleaved in the data. 1.
Chapter 2: Task Guide Setting Up Triggers and Running Measurements "Branches taken" feature of past logic analyzers. The best way to store only the states that cause sequence level branches is by setting up default storing to Nothing, inserting a Store sample action in each sequence level, and inserting a Turn off default storing action in the level that triggers.
Chapter 2: Task Guide Setting Up Triggers and Running Measurements that follow one another, you need to use multiple levels in the trigger sequence. For example, multiple levels in the trigger sequence let you trigger on a particular function calling sequence or capture only the execution within a particular program loop.
Chapter 2: Task Guide Setting Up Triggers and Running Measurements insert. A picture describing the trigger function is shown. 3. Select the Replace button, or select the level button and choose Replace LEVEL. To delete sequence levels 1. In the Trigger tab's Trigger Sequence area, select the level that you want to delete. A yellow box appears around the level. 2. Select the Delete button, or select the level button and choose Delete LEVEL.
Chapter 2: Task Guide Setting Up Triggers and Running Measurements trigger action you want to specify. A yellow box appears around the level. 2. Select the Trigger or Goto button and choose the appropriate Goto or Trigger action. 3. If you chose the Goto or Trigger and goto action, select the level button and choose the appropriate level. Searching for events that trigger the analyzer always starts at the first level. Searching stops after one of the Trigger and fill memory actions.
Chapter 2: Task Guide Setting Up Triggers and Running Measurements 4. In the E-mail Setup dialog, enter the name of the SMTP (see page 76) mail server (if you don't know this, contact your System Administrator), the recipient's e-mail address (use spaces to separate multiple addresses), and the text of the message. If you want e-mail to be sent on each trigger of a repetitive run, select the Send e-mail on repetitive run check box. 5. Select the OK button.
Chapter 2: Task Guide Setting Up Triggers and Running Measurements the protocol. On the Internet, there are the following TCP/IP protocols: • TCP (Transmission Control Protocol), which uses a set of rules to exchange messages with other Internet points at the information packet level. • IP (Internet Protocol), which uses a set of rules to send and receive messages at the Internet address level.
Chapter 2: Task Guide Setting Up Triggers and Running Measurements Editing Advanced Trigger Functions After you break down a trigger function (if it didn't quite provide the trigger capability you need), or after you select one of the advanced trigger functions, you're ready to edit the advanced trigger function. All trigger functions look for events and, if those events are found, take actions.
Chapter 2: Task Guide Setting Up Triggers and Running Measurements 2. Enter a time duration value. The event must be present for the specified period of time before the action is taken. To specify a < duration, break down the Find pattern present for < duration trigger function. (It actually uses occurrence counts and four sequence levels.) To specify an occurrence count for events 1.
Chapter 2: Task Guide Setting Up Triggers and Running Measurements zero), stop (and reset), pause, or resume a timer. You can insert timer events in a different sequence level to test the value of a timer. NOTE: No timer is available for the first pod pair assigned to a logic analyzer. For each additional pod pair assigned to the analyzer, an additional timer is available. To insert a timer action 1.
Chapter 2: Task Guide Setting Up Triggers and Running Measurements and choose either Reset or Increment. To insert a counter event Counter events are like other events in that they evaluate to either true or false. 1. In the Trigger tab's Trigger Sequence area, select one of the existing event buttons (for example, a label name, Anything, Timer, Counter, or Flag) and choose to insert or replace a Counter. 2. Select the counter number button and choose the number of the counter you want to test. 3.
Chapter 2: Task Guide Setting Up Triggers and Running Measurements Flags can also be used to drive the logic analysis system's Port Out signal. To insert a flag action You can use the Set/clear/pulse flag trigger function to insert a flag action. When editing advanced trigger functions, follow these steps to insert a flag action: 1.
Chapter 2: Task Guide Setting Up Triggers and Running Measurements choose to insert or replace a Flag. 2. Select the flag number button and choose the number of the flag you want to test. 3. Select whether you're testing if the flag is Set or Clear. There is approximately 100 ns of delay before a flag action can be seen by a flag event. To drive the Port Out signal with a flag 1. In the main logic analysis system window, select the Port Out button. 2.
Chapter 2: Task Guide Setting Up Triggers and Running Measurements event list, you can specify their evaluation order by grouping the events. 1. In the Trigger tab's Trigger Sequence area, select the If, If not, Else if, or Else if not button, and choose Group events. 2. In the Group Events dialog, either select the Add parens button to group events or select the Remove parens button to ungroup events. 3. Select the OK button.
Chapter 2: Task Guide Setting Up Triggers and Running Measurements Saving/Recalling Trigger Setups You can save a trigger setup within a session by using trigger save/ recall. See Also • “To save a trigger setup” on page 85 • “To recall a trigger setup” on page 85 • “To clear the trigger save/recall list” on page 85 “Save/Recall Subtab” on page 157 To save a trigger setup 1. Set up the trigger. 2. In the Trigger tab's Save/Recall subtab, select the Save button. 3.
Chapter 2: Task Guide Setting Up Triggers and Running Measurements Running Measurements After you set up a trigger, you're ready to run the logic analyzer measurement. • “To start/stop measurements” on page 86 • “If nothing happens when you start a measurement” on page 86 • “To view the trigger status” on page 87 To start/stop measurements To start measurements 1. Select the Run Single , Run Repetitive Group Run Repetitive, or Run All , Group Run Single , button.
Chapter 2: Task Guide Setting Up Triggers and Running Measurements logic analyzer is still running. See Also • Messages such as "Waiting in level 1" may indicate you need to refine your trigger. • If the status shows as "Stopped", the analyzer either finished the acquisition, or was unable to run. The cause of the problem is listed in the bottom half of the Run Status window. • Look for an error message in the message bar at the top of the window.
Chapter 2: Task Guide Displaying Captured Data Displaying Captured Data Once you have run a measurement and filled the logic analyzer's acquisition memory with captured data, you can display the captured data with one of the display tools. You can use analysis tools to filter data and compare data sets. You can also analyze captured data with toolsets like the Serial Analysis Toolset and the System Performance Analysis Toolset.
Chapter 2: Task Guide Displaying Captured Data Waveform and Listing (and other) display tools provide global markers that can be used to correlate data that is captured by different instrument modules or displayed differently in other display tool windows. The Waveform and Listing display tools also give you the ability to search for particular data values captured on labels. Listing displays let you load inverse assemblers that will decode captured data into assembly language mnemonics.
Chapter 2: Task Guide Displaying Captured Data • In Waveform displays, Timing Zoom and the regular data are in different windows. To view them together, select Edit -> Insert from the menu bar. • In Waveform displays, if Timing Zoom and regular data do not correspond, check that the display is set to Seconds/div. Because Timing Zoom has a smaller sample period, when the display is set to Samples/div the data become more divergent the farther from the trigger you scroll.
Chapter 2: Task Guide Displaying Captured Data time. For example, if you use storage qualification (in the state sampling mode) or the Pattern Filter analysis tool, you can chart variable values. You can use the Distribution display tool to show how often different values (among the possible values) are captured on a label. You can use the Compare analysis tool to show the differences between two measurement data sets.
Chapter 2: Task Guide Displaying Captured Data If the captured data doesn't look correct Intermittent Data Errors Check for poor connections, incorrect signal levels on the hardware, incorrect logic levels under the logic analyzer's Config tab, or marginal timing for signals. Unwanted Triggers If you are using an inverse assembler or a pipeline, triggers can be caused by instructions that were fetched but not executed. To fix, add the prefetch queue or pipeline depth to the trigger address.
Chapter 2: Task Guide Displaying Captured Data Since acquisition memory is cleared at the beginning of a measurement, stopping a run may create a discrepancy between acquisition memory and the memory buffer of connected tools. Without a complete trace of acquisition memory, the display memory will appear to have 'holes' in it which appear as filtered data.
Chapter 2: Task Guide Displaying Captured Data • Select the OK button. The symbolic names for the values now appear in the overlaid bus waveform. To view symbolic values in a listing display 1. Select the numeric base of the label where you want to display symbolic values. 2. Set the numeric base to Symbols or Line#. The symbolic names for the values now appear instead of numeric data.
Chapter 2: Task Guide Using Symbols Using Symbols You can use symbol names in place of data values when: • Setting up triggers • Displaying captured data • Searching for patterns in Listing displays • Setting up pattern filters • Setting up ranges in the System Performance Analyzer Symbol names can be: variable names, procedure names, function names, source file line numbers, etc.
Chapter 2: Task Guide Using Symbols To load object file symbols Object files are created by your compiler/linker or other software development tools. 1. Generate an object file with symbolic information using your software development tools. 2. If your language tools cannot generate object file formats that are supported by the logic analyzer, create an ASCII symbol file (see page 100). 3. Select the Symbol tab and then the Object File tab. 4. Select the label name you want to load object file symbols for.
Chapter 2: Task Guide Using Symbols the object file symbols are reloaded. To delete object file symbol files 1. Select the Symbol tab, and then the Object File tab. 2. Select the file name you want to delete in the text box labeled, Object Files with Symbols Loaded For Label. 3. Select Unload. See Also “Symbol File Formats” on page 163 To adjust symbol values for relocated code Use this option to add offset values to the symbols in an object file.
Chapter 2: Task Guide Using Symbols whose symbols you wish to relocate. 3. Select the Relocate Sections... button. 4. Enter the desired offset in the Offset all sections by field. The offset is applied from the linked address or segment. 5. Select Apply Offset. 6. Select Close. To create user-defined symbols 1. Under the Symbol tab, select the User Defined tab. 2. Select the label name you want to define symbols for. 3. At the bottom of the User Defined tab, enter a symbol name in the entry field. 4.
Chapter 2: Task Guide Using Symbols To delete user-defined symbols 1. Under the Symbol tab, select the User Defined tab. 2. Select the label you want to delete symbols from. 3. Select the symbol to delete. 4. Select the Delete button. 5. Repeat steps 3 and 4 to delete other symbols, if desired. To load user-defined symbols If you have already saved a configuration file, and the configuration included user-defined symbols, load the file with its symbols, as follows: 1.
Chapter 2: Task Guide Using Symbols Pattern. • Use the Find Symbols of Type selections to filter the symbols by type. 4. Select the symbol you want to use from the list of Matching Symbols. 5. If you are using object file symbols, you may need to: • Set Offset By (see page 162) to compensate for microprocessor prefetches. • Set Align to x Byte (see page 163) to trigger on odd-byte boundaries. 6. Select the Beginning, End, or Range of the symbol. 7. Select the OK button.
Chapter 2: Task Guide Using Symbols To create a readers.ini file You can change how an ELF/Stabs, Ticoff or Coff/Stabs symbol file is processed by creating a reader.ini file. 1. Create the reader.ini file on your workstation or PC. 2. Copy the file to /logic/symbols/readers.ini on the logic analysis system.
Chapter 2: Task Guide Using Symbols section will be read completely. This can occur if the file was created without a "generate debugger information" flag (usually -g). Using the g will create a Dwarf or Stabs debug section in addition to the ELF section.
Chapter 2: Task Guide Using Symbols C MaxSymbolWidth=60 StabsType=2 Example for Coff/Stabs (using Ticoff reader) [ReadersTicoff] C C MaxSymbolWidth=60 StabsType=2 Example for Ticoff [ReadersTicoff] C C MaxSymbolWidth=60 ReadOnlyTicoffPage=4 AppendTicoffPage=1 103
Chapter 2: Task Guide Printing/Exporting Captured Data Printing/Exporting Captured Data To print captured data You can print captured data from display tool windows. 1. In the display tool window, select Print this window from the File menu. To export captured data You can use the File Out tool to save measurement data to an ASCII format file which can then be imported into a spreadsheet application, a debugger, or some other post-processing tool. 1.
Chapter 2: Task Guide Printing/Exporting Captured Data 5. Select the file name and automatic file sequencing options. 6. Select the Read File button. 7. Drag display, analysis, or toolset icons and drop them on the File In tool icon to view the imported data.
Chapter 2: Task Guide Cross-Triggering Cross-Triggering An instrument must be armed before it can look for a trigger. By default, instruments are set to be armed immediately when you Run the measurement. However, you can set an analyzer instrument to be armed either by the second analyzer within the same instrument (if it's turned on) or by another instrument (in a different slot or frame).
Chapter 2: Task Guide Cross-Triggering 2. Run the measurement. To cross-trigger with another instrument 1. Select the Intermodule button (or from the Window menu, select System and Intermodule). 2. In the Intermodule window, select the icon of the instrument to be armed, and choose the instrument that will arm it. When the logic analyzer waits for the arm signal 1. In the Trigger tab's Trigger Sequence area, select the sequence level that should wait for the other analyzer's trigger. 2.
Chapter 2: Task Guide Solving Logic Analysis Problems Solving Logic Analysis Problems See Also • “To test the logic analyzer hardware” on page 108 • “If nothing happens when you start a measurement” on page 86 • “If the captured data doesn't look correct” on page 92 • “If there are filtered data holes in display memory” on page 92 To test the logic analyzer hardware In order to verify that the logic analyzer hardware is operational, run the Self Test utility.
Chapter 2: Task Guide Solving Logic Analysis Problems If any test fails, contact your local Agilent Technologies Sales Office or Service Center for assistance.
Chapter 2: Task Guide Saving and Loading Logic Analyzer Configurations Saving and Loading Logic Analyzer Configurations The Agilent Technologies 16750A/B logic analyzer settings and data can be saved to a configuration file. The configuration file will include references to any custom trigger libraries you have created, but if the configuration is loaded into an analyzer on a system that does not have the trigger libraries, they will not work correctly.
Chapter 2: Task Guide Saving and Loading Logic Analyzer Configurations NOTE: The Agilent Technologies 16700A/B logic analysis systems can translate configuration files from Agilent Technologies 16500 and 16505A logic analysis systems if the measurement module is the same. If the modules are different, first load the configuration file into a module of the same model number on the new logic analysis system.
Chapter 2: Task Guide Saving and Loading Logic Analyzer Configurations 112
3 Reference • “The Sampling Tab” on page 115 • “The Format Tab” on page 119 • “The Trigger Tab” on page 146 113
Chapter 3: Reference • “The Symbols Tab” on page 159 • “Error Messages” on page 170 • “Specifications and Characteristics” on page 186 114
Chapter 3: Reference The Sampling Tab The Sampling Tab The Sampling tab lets you choose between the logic analyzer's asynchronous sampling Timing Mode or its synchronous sampling State Mode. This tab also lets you set controls for the selected mode as well as Timing Zoom options.
Chapter 3: Reference The Sampling Tab Timing Mode When you select Timing Mode, the Timing Mode Controls area appears. Full/Half Channel Configuration Lets you configure the timing analyzer for faster sampling and greater memory depth, but with half the channels. Trigger Position Lets you specify where the sample that triggered the analyzer should appear among all the other samples that are stored in acquisition memory.
Chapter 3: Reference The Sampling Tab State Mode When you select State Mode, the State Mode Controls area appears. 200 MHz/400 MHz State Speed Configuration Lets you configure the state analyzer for faster sampling, but with clocking restricted to the J clock on Pod 1 of the master card and triggering restricted to two trigger functions. Trigger Position Lets you specify where the sample that triggered the analyzer should appear among all the other samples that are stored in acquisition memory.
Chapter 3: Reference The Sampling Tab under test) that will enable (qualify) the sampling clock. Generally, the state mode sampling clock is taken from the signals that clock valid data in the device under test. The clock channel specifiers graphically show your clock setup. Edges are ORed ("+") together, and qualifiers are ANDed (".") to all edges. To qualify just one of the edges, switch to Advanced Clocking.
Chapter 3: Reference The Format Tab The Format Tab The Format tab lets you assign bus and signal names (from the device under test), to logic analyzer channels. These names are called labels. Labels are used when setting up triggers and displaying captured data. The Format tab also lets you assign pod pairs to one or two logic analyzers, specify the logic analyzer threshold voltage, and adjust the logic analyzer setup/hold (sampling positions).
Chapter 3: Reference The Format Tab clock bits span more than one pod pair.
Chapter 3: Reference Importing Netlist and ASCII Files Importing Netlist and ASCII Files Netlist Files The Netlist Import feature provides a method for importing busses and signals from ASCII netlists created by EDA tools. In order for the feature to work, the device under test must either use the Agilent E5346A high density adapter or the Agilent Technologies Termination Adapter. The adapter must be included as a connector in the netlist. You can create a Netlist file using an EDA tool.
Chapter 3: Reference Importing Netlist and ASCII Files For Example Label1;A2[15:5];A1[5,2] Label1 Bus Name A2 and A1 Pod Numbers [15:5] Channel 15 through Channel 5 ("***********.....") [5,2] Channel 5 and Channel 2 ("..........*..*..") When setting up the ASCII file a comma (",") separates individual channels, while a colon (":") creates a range of channels. The following provides an explanation of how to setup and import ASCII files into a logic analysis system.
Chapter 3: Reference Importing Netlist and ASCII Files Pod A2 Channel 5, and Pod A1 Channel 6. Clocks Label1;CK[AK] Label1 maps to Slot A Clock K. “Importing ASCII Files” on page 123 “Exporting ASCII Files” on page 123 See Also “Termination Adapter” on page 125 “E5346A High Density Adapter” on page 126 Considerations when creating an Import file. When updating a label ensure that the label is turned on. Labels that are not active will not be updated.
Chapter 3: Reference Importing Netlist and ASCII Files To Import an ASCII file. 1. Create an ASCII file for importing into the logic analysis system. For example: Lab2;A2[15:10,6,3] NewLabel2;A2[15] Label1;A1[15:0] 2. Select the Format tab. 3. Select File, then select Import Labels... 4. Select the ASCII file you created. 5. Select OK.
Chapter 3: Reference Importing Netlist and ASCII Files Termination Adapter The logic analyzer cable must have the proper RC network at its input in order acquire data correctly. The Termination Adapter incorporates the RC network into a convenient package. It also reduces the number of pins required for the header on the target board from 40 pins to 20.
Chapter 3: Reference Importing Netlist and ASCII Files E5346A High Density Adapter The E5346A high-density adapter provides a convenient and easy way to connect an Agilent logic analyzer to the signals on your target system for packages that are difficult to probe. An Amp "Mictor 38" connector must be installed on your target system board.
Chapter 3: Reference Importing Netlist and ASCII Files Mapping Connector Names 1. Select the Format tab. 2. Select File, then select Import Netlist. 3. Select Next to go to the Mapping Connector Names dialog. 4. Enter a connector name from the Netlist. 5. Select the type of adapter. 6. Select the logic analyzer pods that are plugged into the adapters. 7. To map more connector names, select Add Connector and repeat the steps above. 8. Select Next. Import the Net List File 1. Select Select Netlist File.
Chapter 3: Reference Importing Netlist and ASCII Files 2. Select the file from the File Selection dialog box. 3. Select OK 4. Select Next Verify Net to Label Mapping 1. Verify that each net was properly imported into a label. 2. Select Next The list provided, see example below, is the mapping from the logic analyzer pods and channels to labels. The label column is editable so you can make changes if necessary. If you need to delete labels, this can be done more efficiently in the next dialog box.
Chapter 3: Reference Importing Netlist and ASCII Files Select/Create Interface Labels Select any additional labels to be copied into the Format tab. Typically there is no need to add any more labels. However, this screen is useful when you want to designate a signal bit in a bus as a separate label name. It can also be used to delete unneeded labels. Once you have completed editing the labels, select Done.
Chapter 3: Reference Importing Netlist and ASCII Files Pod Assignment Dialog Name: Lets you name the analyzers. Type: Lets you select the timing (asynchronous) sampling mode, the state (synchronous) sampling mode, or turn the analyzer off. Pod Pairs Can be dragged-and-dropped under one of the analyzers to assign those channels to the analyzer or can be left unassigned.
Chapter 3: Reference Importing Netlist and ASCII Files Sampling Positions Dialog The Sampling Positions dialog lets you position the logic analyzer's setup/hold window (or sampling position) so that data on high-speed buses is captured accurately, in other words, so that data is sampled when it is valid. When the device under test's data valid window is less than 2.
Chapter 3: Reference Importing Netlist and ASCII Files Eye Finder Option, Setup Tab File menu Lets you save/load eye finder data. EyeFinder menu Lets you run eye finder, choose the run mode, and access the “Eye Finder Advanced Settings Dialog” on page 133. Run Mode Lets you look at eye finder with demo data or in normal operating mode by sampling signals from the device under test. Repetitive Run Runs the eye finder repetitively, so you can see how stable and transitioning signals vary over time.
Chapter 3: Reference Importing Netlist and ASCII Files If a channel appears in multiple labels, selecting that channel will select it in each of those labels. See Also “Understanding State Mode Sampling Positions” on page 208 “To automatically adjust sampling positions” on page 47 Eye Finder Advanced Settings Dialog. Short Eye finder looks at 100,000 clock cycles on each channel to determine the suggested sampling positions. This setting requires frequent transitions on all channels.
Chapter 3: Reference Importing Netlist and ASCII Files Eye Finder Option, Results Tab The Eye Finder Results display is a digital "eye" diagram in that it represents many samples of data captured in relation to the sampling clock. The transitioning edges measured before and after the sampling clock result in a picture that is eye-shaped. You should have already specified the logic analyzer threshold voltage, but you may adjust it to maximize the width of the measured stable regions.
Chapter 3: Reference Importing Netlist and ASCII Files Results menu Let you expand/collapse the signals in a label, set the bus view, set the sampling positions to the suggested sampling positions, and remove all eye finder data. Label buttons Let you expand/collapse the signals in a label, set the bus view, choose the suggested sampling position, and show message or time stamp information. Display Area Shows: • Transitioning (dark) and stable (light) regions on the signals.
Chapter 3: Reference Importing Netlist and ASCII Files How the Selected Position Behaves 1. When eye finder is enabled, the selected position (blue line) is set based on the manual setup/hold value. 2. Whenever the selected position is moved, the manual setup/hold value is also updated. They always track each other. 3. When the manual setup/hold is enabled again, the position changes made while eye finder was enabled can be kept or discarded.
Chapter 3: Reference Importing Netlist and ASCII Files An eye finder measurement is currently running. Stop the eye finder or wait for it to complete before running the eye finder. The eye finder is already running on the other machine defined for this analyzer. Eye finder cannot run on both machines at the same time. "Cannot run the Logic Analyzer at this time." An eye finder measurement is currently running.
Chapter 3: Reference Importing Netlist and ASCII Files "From Eye Finder: After hardware calibration, the sampling positions for the following channels may have shifted out of the selected stable region by the amount shown: CHANNEL: AMOUNT ps ... (NNN more)" Each time a measurement is started, the hardware is re-calibrated. The new calibration values are checked against those used when the eye finder measurements were taken.
Chapter 3: Reference Importing Netlist and ASCII Files request or when the Sampling Positions dialog is closed or iconified. "Timeout: < N K clocks in 5 sec" Eye finder requires stimulus at a minimum rate to perform its measurements. Too few state clocks were seen in the time allotted. Check clock inputs, clock definition, threshold voltage settings, and the operation of the device under test. Eye Finder Info Messages.
Chapter 3: Reference Importing Netlist and ASCII Files 2. The stable region(s) are too small for eye finder to detect. In this case you must resort to adjusting the sample position manually and checking its validity by running an ordinary analyzer measurement to see if the data values you expect are sampled. You can adjust the sample position manually by selecting the arrow buttons or by dragging the blue sampling position indicator in the display. "Only a few transitions detected.
Chapter 3: Reference Importing Netlist and ASCII Files than 5 nsec and the clock period is greater than 10 nsec (slower than 100 MHz). Eye Finder Load/Save Messages. These messages can appear when saving or loading eye finder data. "... (at line XX in the file)" Indicates where the error occurred in the file being read. Since eye finder data files are ASCII text, you can use a text editor to examine the file at the indicated line to determine how to repair the problem.
Chapter 3: Reference Importing Netlist and ASCII Files "Failed to open file for reading/writing: NAME" The selected file could not be opened. Check access and file permissions. "File NAME already exists. Overwrite?" The selected file exists. Answering "Yes" will cause the existing contents of the file to be replaced with current eye finder information. "Invalid true/false flag" The boolean value for the item could not be read. Boolean values start with either a 't' or 'f' ('T' or 'F'are also accepted).
Chapter 3: Reference Importing Netlist and ASCII Files File: Name of the eye finder data file. Created: Date and time the eye finder data file was created. Saved: Date and time the eye finder data file was last saved. You are notified if the eye finder data has changed since the last time it was saved. See Also Load... Loads eye finder data that was previously saved to a file. Reload Reloads eye finder data from the named file, deleting unsaved changes.
Chapter 3: Reference Importing Netlist and ASCII Files Manual Setup/Hold Option When you select Manual Setup/Hold, the following options appear. Label Selection List Lets you select the label whose setup/hold window will be positioned. All bits Specifies that the setting is for all bits on the label. Individual bits Specifies that the setting is for a single bit on the label. Bit: When Individual bits is selected, this field identifies the single bit.
Chapter 3: Reference Importing Netlist and ASCII Files position is after the sampling clock.
Chapter 3: Reference The Trigger Tab The Trigger Tab The Trigger tab is used to tell the analyzer when to capture data. The key event is the trigger. In the Agilent Technologies 16750A/B logic analyzer, you can insert multiple trigger actions. When you insert multiple trigger actions, the trigger marker in the display windows is placed on the first sample whose evaluation caused a branch through an associated trigger action.
Chapter 3: Reference The Trigger Tab • See Also “Save/Recall Subtab” on page 157 “Understanding Logic Analyzer Triggering” on page 192 “Setting Up Triggers and Running Measurements” on page 64 “Editing the Trigger Sequence” on page 72 Trigger Functions Subtab Trigger functions provide a simple way to set up the analyzer to trigger on common events and conditions. A library of functions is available for both state and timing measurements.
Chapter 3: Reference The Trigger Tab General Timing Trigger Functions The following general trigger functions are found in the Trigger Functions tab when the logic analyzer is in the timing sampling mode. You can edit most of the trigger functions to specify particular pattern and edge events. You can break down a trigger function to see how many advanced sequence levels are used. • Find pattern Becomes true when a pattern occurs one time.
Chapter 3: Reference The Trigger Tab • Find 2 edges too close together Becomes true when the second specified edge occurs within a specified time after the first specified edge. • Find 2 edges too far apart Becomes true when the second specified edge does not occur within a specified time after the first specified edge. • Find pattern occurring too soon after edge Becomes true when a specified pattern occurs within a specified time after the first specified edge.
Chapter 3: Reference The Trigger Tab • OR Trigger When the logic analyzer is armed by another instrument (as specified in the Intermodule window), this trigger function becomes true when a pattern occurs a specified number of times OR when the arm signal is received.
Chapter 3: Reference The Trigger Tab This trigger function has been replaced by the "Store range until pattern occurs" and "Store pattern2 until pattern1 occurs" trigger functions. • Store nothing until pattern occurs Becomes true when the specified pattern occurs one time and doesn't store any samples until then. • Run until user stop Sets up to never trigger. You must select the stop button to view the captured data.
Chapter 3: Reference The Trigger Tab Becomes true when the specified pattern occurs in the specified number of samples consecutively. • Find pattern2 n times after pattern1, before pattern3 occurs Becomes true when the second specified pattern occurs in a specified number of samples after the the first specified pattern but without the third specified pattern occurring anywhere in between. • Store n samples Becomes true when the specified number of samples are stored.
Chapter 3: Reference The Trigger Tab “To break down a trigger function” on page 67 “To cross-trigger with another instrument” on page 107 “To cross-trigger between two analyzers” on page 106 Advanced Trigger Functions The advanced trigger functions let you create a custom trigger sequence level using events, comparison functions, and up to 4 branches.
Chapter 3: Reference The Trigger Tab they are specified. The logic analyzer executes the set of actions in the "then" clause associated with the first listed "if" or "else if" clause that becomes true. • Advanced - 4-way branch Like the 3-way branch, but with 3 "Else if" clauses. • Advanced - pattern1 AND pattern2 Searches for two different patterns occurring in the same sample. If you set it to look for more than 1 occurrence, you can specify whether occurrences are consecutive or not.
Chapter 3: Reference The Trigger Tab Trigger Position Lets you specify where the sample that triggered the analyzer should appear among all the other samples that are stored in acquisition memory. Count (State mode only). Lets you save time or state count information with the captured data samples. Arm out from: When two logic analyzers are turned on, this option lets you choose which of them (or both) should drive the arm signal.
Chapter 3: Reference The Trigger Tab Default Storing Subtab Store by default Lets you specify that Anything, Nothing, Custom, or selected Transitions events be stored by default. At start of acquisition Event specification list Group events See Also Lets you choose whether default storing is initially On or Off. When you choose Custom events, this area lets you specify the custom events. When you choose Custom events, you can group events in the list to specify the evaluation order.
Chapter 3: Reference The Trigger Tab Status Subtab The Status subtab shows you the sequence level that is evaluating captured data, occurrence and global counter values, and flag values. See Also “To view the trigger status” on page 87 Save/Recall Subtab The Save/Recall subtab lets you save trigger setups within a session. The Agilent Technologies 16750A/B logic analyzer provides memory locations to store up to 15 trigger sequences for both state and timing sampling modes.
Chapter 3: Reference The Trigger Tab You can also save trigger sequences outside of configuration files by creating trigger function libraries.
Chapter 3: Reference The Symbols Tab The Symbols Tab The Symbols tab lets you load symbol files or define your own symbols. Symbols are names for particular data values on a label. Two kinds of symbols are available: Multiple files • Object File Symbols. These are symbols from your source code and symbols generated by your compiler. • User-Defined Symbols. These are symbols you create.
Chapter 3: Reference The Symbols Tab Object file versions During the load process, a symbol database file with a .ns extension will be created by the system. One .ns database file will be created for each symbol file you load. Once the .ns file is created, the Symbol Utility will use this file as its working symbol database. The next time you need to load symbols into the system, you can load the .ns file explicitly, by placing the .ns file name in the Load This Object/Symbol File For Label field.
Chapter 3: Reference The Symbols Tab Symbols Selector Dialog Search Pattern: Lets you enter partial symbol names and the asterisk wildcard character (*) to limit the symbols to choose from (see “Search Pattern” on page 162). Use the Recall button to select from previous search patterns. Find Symbols of Type Lets you limit the types of symbols to choose from. Matching Symbols Lists the symbols that match the search pattern. You choose a symbol from this list.
Chapter 3: Reference The Symbols Tab Offset By Lets you add an offset value to the starting point of a symbol. This can be useful when compensating for microprocessor prefetches (see “Offset By Option” on page 162). Align to Lets you mask the lower order bits of a symbol's value. This can be useful for triggering on odd byte boundaries (see “Align to x Byte Option” on page 163).
Chapter 3: Reference The Symbols Tab func1 and func2 are adjacent to each other in physical memory, with func2 following func1. In order to trigger on func2 without getting a false trigger from a prefetch beyond the end of func1, you need to add an offset value to your label value. The offset value must be equal to or greater than the prefetch depth of the processor. In this case, you would add an offset of 16 bytes to your label value. You would set the value of the "Offset By" field to 10 hex.
Chapter 3: Reference The Symbols Tab C++ notation. To improve performance for these ELF symbol files, type information is not associated with variables. Hence, some variables (typically a few local static variables) may not have the proper size associated with them. They may show a size of 1 byte and not the correct size of 4 bytes or even more. All other information function ranges, line numbers, global variables and filenames will be accurate. These behaviors may be changed by creating a readers.
Chapter 3: Reference The Symbols Tab The address or address range must be a hexadecimal number. It must appear on the same line as the symbol name, and it must be separated from the symbol name by one or more blank spaces or tabs. Address ranges must be in the following format: beginning address..ending address The following example defines two symbols that correspond to address ranges and one symbol that corresponds to a single address. main test var1 00001000..00001009 00001010..
Chapter 3: Reference The Symbols Tab [START ADDRESS] address #comment text Lines without a preceding header are assumed to be symbol definitions in one of the [VARIABLES] formats. Example This is an example GPA file that contains several different kinds of records. [SECTIONS] prog 00001000..0000101F data 40002000..40009FFF common FFFF0000..FFFF1000 [FUNCTIONS] main 00001000..00001009 test 00001010..0000101F [VARIABLES] total 40002000 value 40008000 4 4 [SOURCE LINES] File: main.
Chapter 3: Reference The Symbols Tab NOTE: If you use section definitions in a GPA symbol file, any subsequent function or variable definitions must be within the address ranges of one of the defined sections. Functions and variables that are not within the range are ignored. Format [SECTIONS] section_name start..end attribute section_name A symbol representing the name of the section. start The first address of the section, in hexadecimal. end The last address of the section, in hexadecimal.
Chapter 3: Reference The Symbols Tab VARIABLES You can specify symbols for variables using: • The address of the variable. • The address and the size of the variable. • The range of addresses occupied by the variable. If you specify only the address of a variable, the size is assumed to be 1 byte. Format [VARIABLES] var_name start [size] var_name start..end var_name A symbol representing the variable name. start The first address of the variable, in hexadecimal.
Chapter 3: Reference The Symbols Tab Example [SOURCE LINES] File: main.c 10 00001000 11 00001002 14 0000100A 22 0000101E See Also Using the Source Viewer (see the Listing Display Tool help volume) START ADDRESS Format [START ADDRESS] address address The address of the program entry point, in hexadecimal. Example [START ADDRESS] 00001000 Comments Use the # character to include comments in a file. Any text following the # character is ignored.
Chapter 3: Reference Error Messages Error Messages • “Analyzer armed from another module contains no "Arm in from IMB" event” on page 185 • “Branch expression is too complex” on page 171 • “Cannot specify range on label with clock bits that span pod pairs” on page 176 • “Counter value checked as an event, but no increment action specified” on page 177 • “Goto action specifies an undefined level” on page 177 • “Hardware Initialization Failed” on page 178 • “Maximum of 32 Channels Per Label” on
Chapter 3: Reference Error Messages Must assign Pod 1 on the master card to specify actions for flags When using a 16760A analyzer in 200Mb/s state mode, Pod 1 on the master card must be assigned in order to add actions for the flags in a branch action list. To assign the pod, go to the format tab and select the "Pod Assignment" button. Drag Pod 1 of the master card from the unassigned pods list to the analyzer assigned list.
Chapter 3: Reference Error Messages NOTE: For labels that do span pod pairs, the complexity can be reduced to the same as that of the non-split label case if all bits in the label on all but one pod pair can be set to Xs in the event list expression for the measurement.
Chapter 3: Reference Error Messages • Cannot AND more than 16 non-split pattern events if the pattern events are all on the same pod pair. • Can AND up to 160 non-split pattern events if the pattern events are evenly distributed across all 10 pod pairs on a 5 card set (16 pattern events per pod pair). Specific Guidelines - 333/400 Mb/s State Modes • Cannot AND or OR more than 8 non-split pattern events if the pattern events are all on the same pod pair.
Chapter 3: Reference Error Messages 1 If (complex event list) occurs 1 time then goto next 2 If anything occurs 1 time then Goto Next 3 If (complex event list) occurs 1 time then Trigger and fill memory • In 333/400 Mb/s State Modes, the trigger sequence compiler must always add some additional complexity to the compiled expression for the first sequence level that is not needed in subsequent sequence levels.
Chapter 3: Reference Error Messages Specific Guidelines - 800 Mb/s State Mode • Labels that span pods (split labels) require more combiner resources than labels with bits that all belong to a single pod. Whenever possible, define labels that do not span pods. In some cases, the compiler will be able to combine 2 non-split labels that are ANDed together even though it fails to compile a pattern on a single label that spans pods. • Cannot specify more than 4 patterns or 2 ranges per pod.
Chapter 3: Reference Error Messages combine 2 non-split labels that are ANDed together even though it fails to compile a pattern on a single label that spans pods. • Cannot specify more than 3 patterns or 1 range per pod. Non-split patterns may use operations: =, !=, <, <=,>, >=, In range, Not in range. Split patterns may only use operations: =, !=. Patterns on labels with re-ordered bits may only use operations: =, != (same as Timing and 200 and 400 Mb/s modes).
Chapter 3: Reference Error Messages Counter value checked as an event, but no increment action specified This warning occurs because you have used a counter in your trigger sequence, but do not have Counter Increment as an action. You do not need to increment the counter in the same sequence level. The counter event will still function, but will not change value. The default value for both counters is 0.
Chapter 3: Reference Error Messages Hardware Initialization Failed Please go to System Administration Tools and run the Self-Test Utility (see page 108) on the logic analyzer. If you have failures, contact your Agilent Technologies Sales Office for service or software upgrades. Must assign another pod pair to specify actions for flags In state sampling mode, when there is only one pod pair assigned to an analyzer, flags are not available.
Chapter 3: Reference Error Messages No more Pattern resources available for this pod pair This error occurs when you have used up all the pattern resources available. Each pod pair has about 28 pattern resources. Some pattern events use more than 1 resource. Possible Solutions • Keep labels within a pod pair If a label (bus) spans pod pairs (for example, pods 2 and 3) then when you use the label in a trigger sequence it will use up at least one pattern resource on both pod pairs.
Chapter 3: Reference Error Messages Slow or Missing Clock The message "Slow or Missing Clock" only appears in state measurements. However, if you have another instrument armed by the state analyzer, a slow or missing clock on the state analyzer will prevent the other instrument from triggering also. Possible Causes • Target system is not running properly Check that the system is running properly.
Chapter 3: Reference Error Messages Resume in any action. You do not need to start the timer in the same sequence level. The timer will still function if not started, but will not change value. Trigger function initialization failure The "trigger function initialization failure" messages mean that you tried to insert a trigger function which required a change to the trigger function default state.
Chapter 3: Reference Error Messages Trigger inhibited during timing prestore The "trigger inhibited" informational message appears when you have a logic analyzer making a conventional timing measurement, and it is set to a slow sample rate. The logic analyzer will fill the designated amount of pre-trigger memory before checking for the trigger condition. To calculate how long this should take, multiply the sample rate by the percentage of pre-trigger memory and the acquisition depth.
Chapter 3: Reference Error Messages expressions must be reduced to 16 and the complexity of some of the expressions may have to also be reduced. Branch expressions that are identical (and simple enough to be combined by a single combiner resource) share the same combiner resource. Reusing identical event list equations where possible will optimize the use of combiner resources (see page 183).
Chapter 3: Reference Error Messages resources). • An inequality compare (<,<=,>,>=) with a split label pattern event requires 2 combiner resources. • A range on a split label pattern event requires 4 combiner resources. • The event list in the custom store qualification dialog also allocates combiner resources from the same pool of 16 resources.
Chapter 3: Reference Error Messages particularly useful when you use store qualifiers to store "no states" (or only the states you are interested in) and the branches taken are stored. • See Also Save the trigger setup, then simplify it to see what part of the sequence does get captured. When you learn what needs to be changed, you can recall the original trigger setup and make changes to it.
Chapter 3: Reference Specifications and Characteristics Specifications and Characteristics NOTE: For a complete comparison of all logic analyzer specifications and characteristics refer to the "Agilent Technologies 16700 Series Logic Analysis System Product Overview".
Chapter 3: Reference Specifications and Characteristics General information - Channel Counts: 1-card module 2-card module 3-card module 4-card module 5-card module 64 data, 4 clock 132 data, 4 clock 200 data, 4 clock 268 data, 4 clock 336 data, 4 clock Probes (at end of flying lead set) - Input Resistance: 100 - Parasitic Tip Capacitance: 1.
Chapter 3: Reference Specifications and Characteristics - Global counters: - Glitch/edge recognizers: Triggering - Maximum Trigger Sequencer Speed: - State Sequence Levels: - Timing Sequence Levels: - Sequence Level Branching: - Maximum Occurrence Count Value: - Pattern Recognizers: - Range Recognizers: - Range Width: - Occurrence Counters: - Global Counters: - Flags: - Flag set/reset to evaluation: - Timers: - Timer Value Range: Timer Resolution: Timer Accuracy: Timer Reset Latency: Glitch/Edge Recognize
Chapter 3: Reference Specifications and Characteristics What is a Specification? A Specification is a numeric value, or range of values, that bounds the performance of a product parameter. The product warranty covers the performance of parameters described by specifications. Products shipped from the factory meet all specifications. Additionally, the products sent to Agilent Technologies Customer Service Centers for calibration and returned to the customer meet all specifications.
Chapter 3: Reference Specifications and Characteristics What is a Function Test? Function tests are quick tests designed to verify basic operation of a product. Function tests include operator's checks and operation verification procedures. An operator's check is normally a fast test used to verify basic operation of a product. An operation verification procedure verifies some, but not all, specifications, and often at a lower confidence level than a calibration procedure.
4 Concepts • “Understanding Logic Analyzer Triggering” on page 192 • “Understanding State Mode Sampling Positions” on page 208 191
Chapter 4: Concepts Understanding Logic Analyzer Triggering Understanding Logic Analyzer Triggering Setting up logic analyzer triggers can be difficult and time-consuming. You could assume that if you know how to program, you should be able to set up a logic analyzer trigger with no difficulty. However, this is not true because there are many concepts that are unique to logic analysis. The purpose of this section is to describe these key concepts and how to use them effectively.
Chapter 4: Concepts Understanding Logic Analyzer Triggering placed on the conveyor belt, and at the other end the boxes fall off. In other words, because logic analyzer memory is limited in depth (number of samples), whenever a new sample is acquired the oldest sample currently in memory is thrown away if the memory is full. This is shown in the following figure.
Chapter 4: Concepts Understanding Logic Analyzer Triggering Special box --------------------- Trigger point ------------------------------ Next: “Summary of Triggering Capabilities” on page 194 Summary of Triggering Capabilities Because logic analyzer triggering provides a great deal of functionality, the following table provides a brief summary of the capabilities covered in this article. Each of these capabilities will be described.
Chapter 4: Concepts Understanding Logic Analyzer Triggering edge before it begins looking for the next rising edge. Because there is a sequence of steps to find the trigger, this is known as a trigger sequence. Each step of the sequence is called a sequence level. Each sequence level consists of two parts; the conditions and the actions. The conditions are Boolean expressions such as “If ADDR = 1000” or “If there is a rising edge on SIG1”.
Chapter 4: Concepts Understanding Logic Analyzer Triggering time. Two sequence levels can never be used to specify two events that happen simultaneously. For example, consider the following trigger sequence: 1. If ADDR = 1000 then Go to 2 2. If DATA = 2000 then Trigger If the following samples were acquired, the logic analyzer would trigger on sample #7.
Chapter 4: Concepts Understanding Logic Analyzer Triggering analyzer will never trigger. When the conditions are met in a sequence level, it is clear which sequence level will be executed next when a “Go To” action is used, but it is not necessarily clear if there is no “Go To”. On some logic analyzers, if there is no “Go To”, this means that the next sequence level should be executed. On other logic analyzers, it means the same sequence level should be executed again.
Chapter 4: Concepts Understanding Logic Analyzer Triggering Branches Branches are similar to the Switch statement in the C programming language and the Select Case statement in Basic. They provide a method for testing multiple conditions. Each branch has its own actions. An example of multiple branches is shown below: 1. If ADDR < 1000 then Go To 2 Else If ADDR > 2000 then Go To 3 Else If DATA = 2000 then Trigger 2. If DATA <= 7000 then Trigger 3.
Chapter 4: Concepts Understanding Logic Analyzer Triggering “not in range” function as well. Ranges are a convenient shortcut so that you don't have to specify “ADDR >= 1000 and ADDR <= 2000”. Next: “Flags” on page 199 Flags Flags are Boolean variables that are used to send signals from one module to another. They can be set when a condition occurs in one module and tested later by another module.
Chapter 4: Concepts Understanding Logic Analyzer Triggering be used in place of Global Counters, if possible, because they are easier to use and because there is a limited number of Global Counters. Next: “Timers” on page 200 Timers Timers are used to check the amount of time that has elapsed between events. For example, if you want to trigger on one edge followed by another edge that occurs within 500ns, use a timer.
Chapter 4: Concepts Understanding Logic Analyzer Triggering because timer1 will keep running and condition “Timer1 <500 ns” will never be met. There might be another rising edge on SIG1 that is followed within 500ns by the rising edge on SIG2 that occurs later on, so this situation is unacceptable. To fix this problem, whenever the timer exceeds 500ns without triggering, the sequence should loop back to Level 1 to look for another rising edge on SIG1.
Chapter 4: Concepts Understanding Logic Analyzer Triggering ADDR In Range 1000 to 2000 By default, the Default Storage is set to store all samples acquired. You can also set the Default Storage to store nothing, which means that no samples will be stored unless a sequence level overrides the default storage. Sequence Level Storage Sequence level storage qualification means that within a particular sequence level only certain samples will be stored.
Chapter 4: Concepts Understanding Logic Analyzer Triggering 1. If DATA Else If Store Go to Else If Don't Go to = 005E then Trigger ADDR in range 5000 to 6FFF then Sample 1 ADDR not in range 5000 to 6FFF then Store Sample 1 Alternatively, if the default storage is set to “Store Everything”, use the following: 1.
Chapter 4: Concepts Understanding Logic Analyzer Triggering The Agilent 16715A trigger user interface Note that a picture (which corresponds to the selected function) is provided to the right of the trigger function list. For example, if you want to trigger when a bus pattern is immediately followed by another bus pattern, you can use the “Find Pattern2 occurring immediately after Pattern1” trigger function, shown in the following figure.
Chapter 4: Concepts Understanding Logic Analyzer Triggering The same trigger as If/Then statements Trigger functions can be modified. For example, if you start with the function “Find Edge”, you can add another event, and it becomes the same as “Find Edge and Pattern”. Therefore, a function that is not exactly correct can often be converted into the desired trigger. It is also possible to break down a function into the underlying If/Then statements and modify them.
Chapter 4: Concepts Understanding Logic Analyzer Triggering “Find Edge” and “Find Pattern” together Next: “Setting Up Complex Triggers” on page 206 Setting Up Complex Triggers Frequently, the most difficult part of setting up a complex trigger is breaking down the problem. In other words, how do you map a complex trigger into sequence levels, branches, and Boolean expressions? Here are step by step instructions: 1. Break down the problem into events that don't happen simultaneously.
Chapter 4: Concepts Understanding Logic Analyzer Triggering different parts of the trigger to describe how they work. Inline documentation on an Agilent logic analyzer Next: “Conclusions” on page 207 Conclusions Setting up logic analyzer triggers is very different than writing software. The job can be greatly simplified if other work can be leveraged by using pre-defined trigger functions and well-documented triggers that were written earlier.
Chapter 4: Concepts Understanding State Mode Sampling Positions Understanding State Mode Sampling Positions Synchronous sampling (state mode) logic analyzers are like edgetriggered flip-flops in that they require input logic signals to be stable for a period of time before the clock event (setup time) and after the clock event (hold time) in order to properly interpret the logic level. The combined setup and hold time is known as the setup/hold window.
Chapter 4: Concepts Understanding State Mode Sampling Positions To position the setup/hold window (sampling position) within the data valid window, a logic analyzer has an adjustable delay on each sampling clock input (to position the setup/hold window for all the channels in a pod). Sample Position Adjustments on Individual Channels Some logic analyzers let you adjust the position of the setup/hold window (sampling position) on each channel.
Chapter 4: Concepts Understanding State Mode Sampling Positions channel in a small fraction of the time (and without the extra test equipment) that it takes to make the adjustments manually. Eye finder is an easy way to get the smallest possible logic analyzer setup/hold window.
Glossary absolute Denotes the time period or count of states between a captured state and the trigger state. An absolute count of -10 indicates the state was captured ten states before the trigger state was captured. acquisition Denotes one complete cycle of data gathering by a measurement module. For example, if you are using an analyzer with 128K memory depth, one complete acquisition will capture and store 128K states in acquisition memory.
Glossary pointing device, to click an item, position the cursor over the item. Then quickly press and release the left mouse button. clock channel A logic analyzer channel that can be used to carry the clock signal. When it is not needed for clock signals, it can be used as a data channel, except in the Agilent Technologies 16517A.
Glossary instrument tool. Multiple data sets can be displayed together when sourced into a single display tool. The Filter tool is used to pass on partial data sets to analysis or display tools. debug mode See monitor. delay The delay function sets the horizontal position of the waveform on the screen for the oscilloscope and timing analyzer. Delay time is measured from the trigger point in seconds or states. demo mode An emulation control session which is not connected to a real target system.
Glossary Using the Touchscreen: Position your finger over the item, then press and hold finger to the screen. While holding the finger down, slide the finger along the screen dragging the item to a new location. When the item is positioned where you want it, release your finger. edge mode In an oscilloscope, this is the trigger mode that causes a trigger based on a single channel edge, either rising or falling. edge terms Logic analyzer trigger resources that allow detection of transitions on a signal.
Glossary logic analyzer what data you want to collect, such as which channels represent buses (labels) and what logic threshold your signals use. frame The Agilent Technologies or 16700A/B-series logic analysis system mainframe. See also logic analysis system. gateway address An IP address entered in integer dot notation. The default gateway address is 0.0.0.0, which allows all connections on the local network or subnet.
Glossary is usually represented as decimal numbers separated by periods; for example, 192.35.12.6. Ask your LAN administrator if you need an internet address. labels Labels are used to group and identify logic analyzer channels. A label consists of a name and an associated bit or group of bits. Labels are created in the Format tab. line numbers A line number (Line #s) is a special use of symbols.
Glossary machine because the master card is in slot C of the mainframe. The other cards of the module are called expansion cards. menu bar The menu bar is located at the top of all windows. Use it to select File operations, tool or system Options, and tool or system level Help. message bar The message bar displays mouse button functions for the window area or field directly beneath the mouse cursor. Use the mouse and message bar together to prompt yourself to functions and shortcuts.
Glossary by the channel width of the instrument. pod See pod pair point To point to an item, move the mouse cursor over the item, or position your finger over the item. preprocessor See analysis probe. primary branch The primary branch is indicated in the Trigger sequence step dialog box as either the Then find or Trigger on selection. The destination of the primary branch is always the next state in the sequence, except for the Agilent Technologies 16517A.
Glossary measurement as part of its data acquisition cycle. Sampling Use the selections under the logic analyzer Sampling tab to tell the logic analyzer how you want to make measurements, such as State vs. Timing. secondary branch The secondary branch is indicated in the Trigger sequence step dialog box as the Else on selection. The destination of the secondary branch can be specified as any other active sequence state. See also primary branch.
Glossary symbols Symbols represent patterns and ranges of values found on labeled sets of bits. Two kinds of symbols are available: • Object file symbols - Symbols from your source code, and symbols generated by your compiler. Object file symbols may represent global variables, functions, labels, and source line numbers. • User-defined symbols - Symbols you create. Symbols can be used as pattern and range terms for: • Searches in the listing display.
Glossary timing measurement In a timing measurement, the logic analyzer samples data at regular intervals according to a clock signal internal to the timing analyzer. Since the analyzer is clocked by a signal that is not related to the system under test, timing measurements capture traces of electrical activity over time. These measurements are asynchronous with the test system.
Glossary field. This action allows you to select specific portions of a particular waveform in acquisition memory that will be displayed on the screen. You can view any portion of the waveform record in acquisition memory.
Index Symbols &, 78 *, bit assignment, 59 +, label polarity, 61 -, label polarity, 61 ., bit unassignment, 59 Numerics 1.25 ns sample rate, 41 16750A/B 400 MHz State/2 GHz Timing Zoom Logic Analyzer, 2 16750A/B characteristics, 186 16750A/B specifications, 186 2 GHz Timing Zoom, 54 2.
Index clock channels, inputs available as data, 119 clock qualifier, 14 clock qualifiers, characteristic, 186 clock setup, 14 clock setup area, 117 clock speeds and sampling positions, 43 clock threshold level note, 58 clock threshold note, 44 clock time, specification, 186 code, assigning address offsets, 97 COFF symbol reader options, 102 comments, 169 Compare analysis tool, 90 complex triggers, 206 compressing a trigger function, 67 configuration files, 11 configuration files, loading, 110 configuration
Index errors in data, 92 evaluation order, 83 event evaluation order, 83 event list, naming, 84 events, 20, 78 events, counter, 80 events, flag, 81, 149, 152 events, grouping, 83 events, label edge, 66 events, label pattern, 66 events, timer, 79 eventual occurrence counts, 78 example, 162, 163 expanding a trigger function, 67 expansion frames, using flags, 81 exporting captured data, 104 expressions, boolean, 197 eye finder, 43, 47, 132, 208 eye finder advanced settings, 133 eye finder data, 110 eye finder
Index in symbol browser, 162 increment counter, 80 information, for more, 24 input capacitance, probe, characteristic, 186 input resistance, probe, characteristic, 186 inserting a named event, 84 inserting labels, 59 inserting trigger sequence levels, 73 instruments, triggering other, 106 Intermodule window, 81, 107 inverse assemblers, 88 L label edge events, 66 label pattern events, 66 label polarity, 61 label values, 66 label values, symbolic, 99 labels, 20, 57 labels, assigning channels to, 59 labels, a
Index patterns, 66 pause timer, 79 performance verification, 108 period, sample, 42 pod assignment dialog, 57 pod clocking, demultiplex, 44 pod pairs, assigning, 17 pod thresholds, setting, 58 pods, assigning, 57 pods, specifying state clock, 44 polarity, label, 61 Port Out, using flags to drive, 81 positive logic, 61 power through pod cables, characteristic, 186 predefined trigger functions, 147 prefetch, triggering beyond, 162 present for >, 78 preserving bit assignments, 62 previous trigger setup, recal
Index skew, channel-to-channel, characteristic, 186 slave clocks for pods, 44 slow clock message, 180 SMTP, 76 soft shutdown option, 53 source line numbers, 168 source viewer, 88 specifications and characteristics, 186 speed, state/timing, characteristic, 186 SSTL2 threshold level, 58 SSTL3 threshold level, 58 stable regions, 135 Stabs symbol reader options, 102 standard buses, probing, 13 standard lead set, 13 start address, 169 start timer, 79 start trigger position, 52 starting measurements, 86 state an
Index timing trigger functions, 147 timing trigger functions, general, 148 Timing Zoom data, 89 timing, memory depth, 41 transitional timing, 37 transitional timing considerations, 39 trigger and send e-mail, 75 trigger characteristics, 186 trigger function libraries, 68 trigger function, breaking down, 67 trigger function, compressing, 67 trigger function, expanding, 67 trigger functions, 65, 203 trigger functions, advanced, 153 trigger functions, branching, 74 trigger functions, general state, 150 trigge
Index 230
Publication Number: 5988-9040EN January 1, 2003 s1
