user manual
Table Of Contents
- Agilent Technologies 16750A/B Logic Analyzer
- Agilent Technologies 16750A/B Logic Analyzer
- Contents
- Getting Started
- Step 1. Connect the logic analyzer to the device under test
- Step 2. Choose the sampling mode
- Step 3. Format labels for the probed signals
- Step 4. Define the trigger condition
- Step 5. Run the measurement
- Step 6. Display the captured data
- For More Information...
- Example: Timing measurement on counter board
- Example: State measurement on counter board
- Task Guide
- Probing the Device Under Test
- Choosing the Sampling Mode
- To select transitional timing or store qualified
- Formatting Labels for Logic Analyzer Probes
- Setting Up Triggers and Running Measurements
- Displaying Captured Data
- Using Symbols
- Printing/Exporting Captured Data
- Cross-Triggering
- Solving Logic Analysis Problems
- Saving and Loading Logic Analyzer Configurations
- Reference
- The Sampling Tab
- The Format Tab
- Importing Netlist and ASCII Files
- The Trigger Tab
- The Symbols Tab
- Error Messages
- Must assign Pod 1 on the master card to specify actions for flags
- Branch expression is too complex
- Cannot specify range on label with clock bits that span pod pairs
- Counter value checked as an event, but no increment action specified
- Goto action specifies an undefined level
- Maximum of 32 Channels Per Label
- Hardware Initialization Failed
- Must assign another pod pair to specify actions for flags
- No more Edge/Glitch resources available for this pod pair
- No more Pattern resources available for this pod pair
- No Trigger action found in the trace specification
- Slow or Missing Clock
- Timer value checked as an event, but no start action specified
- Trigger function initialization failure
- Trigger inhibited during timing prestore
- Trigger Specification is too complex
- Waiting for Trigger
- Analyzer armed from another module contains no "Arm in from IMB" event
- Specifications and Characteristics
- Concepts
- Understanding Logic Analyzer Triggering
- Understanding State Mode Sampling Positions
- Getting Started
- Glossary
- Index
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Chapter 2: Task Guide
To select transitional timing or store qualified
saved into one sample of logic analyzer memory.
Two additional sampling clock modes let you capture data differently:
•In the Master/Slave mode, you can save data captured on different clock
edges into the same sample of logic analyzer memory.
When the slave clock occurs, data captured on the pods that use the slave
clock is saved in a slave latch. Then, when the master clock occurs, data
captured on the pods that use the master clock, as well as the slave latch
data, are saved into logic analyzer memory.
•In the Demultiplex mode, you can demultiplex data being probed by one
pod into the logic analyzer memory that is normally used for two pods.
When the slave clock occurs, data captured on the pod is saved into the
slave latch for the other pod in the pod pair. Then, when the master clock
occurs, data captured on the pod, as well as the slave latch data, are saved
in logic analyzer memory.
To set up the master sampling clock mode
1. In the Sampling tab, with State Mode selected, select the Master only
mode in the Clock Setup area.