Technical Specs

Product Technical Specification
Rev 3 Oct.20 28 41113694
SIM Implementation
Note: For interface design requirements, refer to ETSI TS 102 230 V5.5.0, section 5.2.
When designing the remote SIM interface, you must make sure that SIM signal integrity is
not compromised.
Some design recommendations include:
• Total impedance of the VCC and GND connections to the SIM, measured at the
module connector, should be less than 1  to minimize voltage drop (includes any
trace impedance and lumped element components—inductors, filters, etc.).
• Position the SIM connector 10 cm from the module. If a longer distance is required
because of the host device design, use a shielded wire assembly—connect one end
as close as possible to the SIM connector and the other end as close as possible to
the module connector. The shielded assembly may help shield the SIM interface from
system noise.
• Reduce crosstalk on the UIM1_DATA and UIM2_DATA lines to reduce the risk of
failures during GCF approval testing.
• Avoid routing the clock and data lines for each SIM (UIM1_CLK/UIM1_DATA,
UIM2_CLK/UIM2_DATA) in parallel over distances 2 cm—cross-coupling of a clock
and data line pair can cause failures.
• 3GPP has stringent requirements for I/O rise time (<1 µs), signal level limits, and
noise immunity—consider this carefully when developing your PCB layout.
· Keep signal rise time <1 µs—keep SIM signals as short as possible, and keep very
low capacitance traces on the data and clock signals (UIM1_CLK, UIM1_DATA,
UIM2_CLK, UIM2_DATA). High capacitance increases signal rise time, potentially
causing your device to fail certification tests.
• Add external pull-up resistors (15 k–30 k), if required, between the data and power
lines for each SIM (UIM1_DATA/UIM1_PWR, UIM2_DATA/UIM2_PWR) to optimize
the signal rise time.
• VCC line should be decoupled close to the SIM socket.
• SIM is specified to run up to 5 MHz (SIM clock rate). Take note of this speed in the
placement and routing of the SIM signals and connectors.
• You must decide whether additional ESD protection is required for your product, as it
is dependent on the application, mechanical enclosure, and SIM connector design.
The SIM pins will require additional ESD protection if they are exposed to high ESD
levels (i.e. can be touched by a user).
• Putting optional decoupling capacitors on the SIM power lines (UIM1_PWR,
UIM2_PWR) near the SIM sockets is recommended—the longer the trace length
(impedance) from the socket to the module, the greater the capacitance requirement
to meet compliance tests.
• Putting an optional series capacitor and resistor termination (to ground) on the clock
lines (UIM1_CLK, UIM2_CLK) at the SIM sockets to reduce EMI and increase signal
integrity is recommended if the trace length between the SIM socket and module is
long—47 pF and 50  resistor are recommended.
• Test your first prototype host hardware with a Comprion IT
3
SIM test device at a
suitable testing facility.