Service manual

SERVICE MANUAL
23
Signal name Dir Explanation
/FP2_PROG out For configuration to FPGA on ADAT PCB.
PLD2_TMS
PLD2_TDI
out For configuration to CPLD on DIO.
PLD2_TDO in For configuration to CPLD on DIO.
TCK,TMS,TDI in For configuration.(TCK is also used for CPLD on DIO)
TDO out For configuration.
VCCINT - Positive supply for internal logic. +3.3V
VccIO - Positive supply for output driver. +3.3V
GND - Ground supply.
1-7. IC9 XC2S100-5TQ144C (Field Programmable Gate Arrays (FPGA))
IDE controller.
DMA controller between Voice-LSI and IDE/SCSI.
MIDI interface.
1-7-2. Pin Descriptions
Signal name Dir Explanation
CD[15:0] i/o Connected with CPU bus for communication.
A[5:0] in Connected with CPU address bus for communication.
/IDE_CS in Chip select for this FPGA.
/CPU_RD in Data output enable of CPU bus.
/CPU_WR in Data strobe of CPU bus.
RESET in Initialize FPGA logic. Active high.
LSI_D[15:0] i/o Connected with DMA data bus of Voice-LSI.
IDE_D[15:0] i/o Connected with data bus of IDE.
IDE_DA[2:0] out Connected with DA[2:0] of IDE I/F
/IDE_CS1,0 out Connected with CS[1:0] of IDE I/F.
/IDE_IORD Out Connected with /DIOR_HD of IDE I/F.
/IDE_DIOW Out Connected with /DIOW_STOP of IDE I/F.
IORDY in Connected with IORDY of IDE I/F.
/IDE_DMACK out Connected with /DMACK of IDE I/F.
IDE_DMARQ in Connected with DMARQ of IDE I/F.
CPU_RDY out Connected with CPU RDY.
SCSI_DMAREQ in Connected with SCSI controller. DMA control.
/SCSI_DMACK out Connected with SCSI controller. DMA control.
LSI_DMAREQ out Connected with Voice-LSI. DMA control.
/LSI_DMAACK in Connected with Voice-LSI. DMA control.
/LSI_DMARD in Connected with Voice-LSI. DMA control.
/LSI_DMAWR in Connected with Voice-LSI. DMA control.
/INT_DMA out Interrupt request output of DMA to CPU. Active low.
LRCK in Word clock of system. Connected with Voice-LSI.
SFrame out Pin No.133. Frequency= Fs/256. duty cycle= 255:1.
MIDI_IN1,2 in MIDI 2 input.
MIDI_OUT1-4 out MIDI 4 output.
/INT_MIDI out Interrupt request output of Midi to CPU. Active low.
MCLK in Master clock of FPGA logic.
CCLK in Configuration clock I/O pin.
/INIT i/o For configuration. Active Low.
/PROGRAM in Initiates a configuration sequence when asserted Low.
DONE i/o Indicates that configuration is complete. open drain.
M0,M1,M2 in configuration mode pin.
TCK,TMS,TDI in # Not used though this is connected #
VCCINT - Power supply for internal core logic. +2.5V
VccO - Power supply for output driver. +3.3V
GND - Ground supply.