Specifications

800-TEC-ENGR
www.avg.net
A-26
Position Transducers/Sensors
DM5 SPECIFICATIONS
Input Power:
AC:
105-135 VAC or 210-270 VAC, 50/60 Hz, 5 W
DC: 8-30 VDC @ 0.25 A exclusive of load (without optical
isolation, an external power supply is needed only for PNP
outputs)
Operating Temperature: -10 °F to +130 °F (-23 °C to +55 °C)
Position Transducer: AVG Automation's RL100, E7R, E8R, or
RL101 single-turn resolvers.
Output Format and Resolution:
BCD:
0360, 1000 or 3600 counts-per-turn
Natural Binary: 1000, 1024, 3600, 4096, or 8192 counts-per-
turn
Gray code: 0256, 0360, 0512, 1000, 1024, 3600, 4096, or 8192
counts-per-turn
Maximum Cable Length between Resolver and DM5: 2500 ft,
shielded
Resolver shaft speed: 3600 RPM (max.)
Resolver-to-digital decoder tracking speed: 1800 RPM
Display: 3- or 4-digits, 0.3" (7.62 mm) LEDS
Offset Capability: Programmable full scale
PLC Synch Circuit (optional):
Input Logic:
0 to 24 VDC logic
Logic False: 0 to 0.8 V @ 3.2 mA
Logic True: 2.4 V @ 0.4 mA, Positive- and negative-edge
triggered.
PC Handshake strobe: 30 µs minimum width
Data Latch Delay: Adjustable 200 µs to 30 ms. Factory set at
3 ms ±20%
Optical Isolation (optional): 2500 Volts, on all I/Os except
resolver
Output
Type
T:TTL *
(74LS645)
P: PNP Source
Transistor
(Sprague UDN-2981A)
N: NPN Sink
Transistor
Low TRUE
(Sprague ULN-2803A)
C: NPN Sink
Transistor
High TRUE
(Sprague ULN-2803A)
Logic TRUE
2 VDC @ 15 mA 2.4 V @ 3 mA
(20 µA leakage when Tristated)
Transistor ON
1.7 V drop @ 100 mA
Transistor ON
1.1 V @ 100 mA
Collector Open
0.1 mA leakage @ 50 VDC
Logic FALSE
0.35 V @ 24 mA
(0.4 mA leakage when Tristated)
Transistor OFF
0.2 mA leakage @ 50 VDC
Collector Open
0.1 mA leakage @ 50 VDC
Transistor ON 1.1 V @ 100 mA
* Note: Multiplexing or Tristating Input = Low active TTL level (i.e., Logic TRUE: 0-0.8 V; Logic FALSE: 2 VDC)