Specifications

800-TEC-ENGR
www.avg.net
A-34
Position Transducers/Sensors
DMM SPECIFICATIONS
Input Power:
AC:
105-135 V or 210-270 V, 50/60 Hz, 5 W
DC: 8 -30 VDC @ 0.25 A, exclusive of load (without using
optical isolation, an external power supply is needed only for
PNP outputs)
Operating Temperature: -10 °F to +130 °F (-2 °C to +55 °C)
Position Transducer: AVG Automation's RL100, E7R, E8R, or
RL101 single-turn resolvers.
Maximum Cable Length between Resolver and DMS: 2500 ft
(762 m), shielded twisted-pair
Output Format and Resolution:
BCD:
360, 1000, or 3600 counts-per-turn
Natural Binary: 1000, 1024, 3600 or 4096 counts-per-turn
Gray code: 256, 360, 512, 1000, 1024, 3600, or 4096 counts-
per-turn
Resolver shaft speed: 3600 RPM (max.)
Resolver-to-digital decoder tracking speed: 1800 RPM
Display: 3 or 4 digits, 0.25" (6.35 mm) LEDs
PLC Sync. Input: (option)
Positive-edge: (LOW to HIGH) and
Negative-edge: (HIGH to LOW) triggered.
(See Input Logic for Voltage and Current specification: )
PC-handshake strobe: 30 µs minimum width
Strobe Delay to Latch Data: 100 µs
Transparent Mode/Microfreeze (Standard):
Output data is continuously updated at full speed. The data is
latched for 100 ±10 µs within 30 µs of a transition (HIGH to
LOW or LOW to HIGH) at data transfer input.
Optical Isolation (Optional):
2500 Volts, on all I/Os except
resolver
Input Logic (Channel Select, PLC Sync; Gear Select):
28 VDC Max:
P-type:
Logic FALSE:
0 to 0.8 V @ 4 mA;
Logic TRUE: 2.4 V @ 3.2 mA
N-type:
Logic FALSE:
3.8 V @ 0.4 mA;
Logic TRUE: 0 to 0.8 V @ 3.2 mA
C-type:
Logic FALSE:
0 to 0.8 V @ 3.2 mA;
Logic TRUE: 3.8 V @ 0.4 mA
0 to 5 VDC Logic:
T-type:
Logic FALSE:
0 to 0.8 V @ 3.2mA;
Logic TRUE: 2.4 V @ 0.4 mA
Channel Select Timing:
Input Multiplexing: 100 ms from channel select
Output Multiplexing: 15 µs from channel select
Gear Select Timing: 15 µs from gear ratio select input
Output
Type
T:TTL *
(74LS645)
P: PNP Source
Transistor
(Sprague UDN-2981A)
N: NPN Sink
Transistor
Low TRUE
(Sprague ULN-2803A)
C: NPN Sink
Transistor
High TRUE
(Sprague ULN-2803A)
Logic TRUE
2 VDC @ 15 mA 2.4 V @ 3 mA
(20 µA leakage when Tristated)
Transistor ON
1.7 V drop @ 100 mA
Transistor ON
1.1 V @ 100 mA
Collector Open
0.1 mA leakage @ 50 VDC
Logic FALSE
0.35 V @ 24 mA
(0.4 mA leakage when Tristated)
Transistor OFF
0.2 mA leakage @ 50 VDC
Collector Open
0.1 mA leakage @ 50 VDC
Transistor ON 1.1 V @ 100 mA
* Note: Multiplexing or Tristating Input = Low active TTL level (i.e., Logic TRUE: 0-0.8 V; Logic FALSE: 2 VDC)