Specifications

800-TEC-ENGR
www.avg.net
A-44
Position Transducers/Sensors
M1150-M10 SPECIFICATIONS
Input Power:
AC:
120 VAC ±10%, 7 VA; Optional 220, 240 VAC
DC: 11-28 VDC, 100 mA (typical) exclusive of load
Operating Temperature: -10 °F to 130 °F (-23 °C to 55 °C)
Position Transducer: AVG Automation's series RL100, E6R, E7R,
E8R, or RL101 resolvers
Signal Resolution: 4096 counts/turn
Scale Factor: 0.300-4095.999, programmable
Output Update rate: 1.4 ms
Preset: 6 digits
Decimal Point: Fully Programmable
Resolver Cable length: 2500 ft. (762 m) max., shielded
OUTPUTS: (All outputs have to be same type)
Type of Outputs: T, P, N, or C
T: LS TTL (74LS645):
Logic TRUE:
2 VDC @ 15 mA, 20 mA leakage, when tristated
Logic FALSE: 0.35 V @ 24 mA, 0.4 mA leakage, when tristated
MUX Input: Low active TTL level
Logic TRUE: 0-0.8 V
Logic FALSE: 2-5 V
P: PNP (sourcing) transistor:
Logic TRUE:
Transistor ON, 1.7 V drop @ 100 mA
Logic FALSE: Transistor OFF, 0.2 mA leakage @ 50
N: NPN (sinking) transistor:
Logic TRUE:
Transistor ON, 1.1 V max. @ 100 mA
Logic FALSE: Transistor OFF, 0.1 mA leakage @ 50 V
C: NPN (sinking) transistor:
Logic TRUE:
Transistor OFF, 0.1 mA leakage @ 50 V
Logic FALSE: Transistor ON, 1.1 V max. @ 100 mA
Output Format: BCD
Motion Outputs: Logic TRUE when shaft within programmed
limits
Output Isolation: All outputs optically isolated up to 2500 V
INPUTS:
Program Enable Input, Preset Input, Output Enable Input
N, C, T:
Enable:
0.8 V max. @ 5 mA
Disable: 4-28 VDC
P:
Enable:
11 to 28 VDC max. @ 13.5 mA max.
Disable: 2 V or open-circuit
Data Transfer Input: 0 to 28 VDC logic; Edge triggered (i.e., data
transfer on both rising and falling edges)
Low Level: 0 to 0.8 V @ 3.2 mA
High Level: 2.4 V @ 0.4 mA
Minimum pulse width: 30 µs
Timing: Depends upon the PC sync option selected from
keyboard
PC Synchronization mode: Updates position output within 150
µs of a transition edge (LOW-to-HIGH, or HIGH-to-LOW) at
data transfer input.
Transparent Mode/Microfreeze: Output data are continuously
updated at full speed.The data are latched for 100 µs ±10%
within 10 µs of a transition (HIGH-to-LOW or LOW-to-HIGH)
at data transfer input.