Datasheet

Figure 29. Burst write followed by burst read:
RL=5 (AL=2, CL=3, WL=4, t
WTR
=2, BL=4)
CK#
CK
CKE
T0 T1 T4 T5 T6 T7 T8 T9T2 T3
NOP NOP NOP NOP
Post CAS#
READ A
NOP NOP NOP NOP
DQS
AL=2
DQS#
WL = RL-1 = 4
DQS#
DQS
CL=3
RL=5
>=t
WTR
DNA
0
DNA
1
DNA
2
DNA
3
DOUT A
0
DQ
NOTE : The minimum number of clock from the burst write command to the burst read command is [CL-1 + BL/2 + t
WTR
].
This t
WTR
is not a write recovery time (t
WR
) but the time required to transfer the 4 bit write data from the input buffer into
sense amplifiers in the array. t
WTR
is defined in the timing parameter table of this standard.
Write to Read = CL-1+BL/2+t
WTR
Figure 30. Seamless burst write operation RL=5, WL=4, BL=4
CK#
CK
CMD
T0 T1 T4 T5 T6 T7 T8T2 T3
Post CAS#
Write A
NOP
Post CAS#
Write B
NOP NOP NOP NOP NOP NOP
DQS
DQS#
WL = RL-1 = 4
DQS#
DQS
DNA
0
DNA
1
DNA
2
DNA
3
DQ
DNB
0
DNB
1
DNB
2
DNB
3
NOTE : The seamless burst write operation is supported by enabling a write command every other clock for
BL= 4 operation, every four clocks for BL = 8 operation. This operation is allowed regardless of same or
different banks as long as the banks are activated.
AS4C128M16D2A-25BCN
AS4C128M16D2A-25BIN
Confidential
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Rev.1.0 Dec 2015