AS4C16M16MD1 256Mb MOBILE DDR SDRAM TABLE OF CONTENTS 1. GENERAL DESCRIPTION ................................................................................................... 4 2. FEATURES........................................................................................................................... 4 3. PIN DESCRIPTION............................................................................................................... 5 3.1 Signal Descriptions........................................
AS4C16M16MD1 256Mb MOBILE DDR SDRAM 8.1 Absolute Maximum Ratings ..........................................................................................................43 8.2 Input/Output Capacitance ............................................................................................................. 43 8.3 Electrical Characteristics and AC/DC Operating Conditions ........................................................ 44 8.3.1 Electrical Characteristics and AC/DC Operating Conditions..........
AS4C16M16MD1 256Mb MOBILE DDR SDRAM Revision History 256M AS4C16M16MD1- 60-ball FPBGA PACKAGE Revision Rev 1.0 Rev 1.1 Details Preliminary datasheet Temperature Changed from -25 to -30°C to +85°C Date Mar 28, 2013 Oct 24, 2015 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 3/56 - Ver.1.1 Oct.
AS4C16M16MD1 256Mb MOBILE DDR SDRAM 1. GENERAL DESCRIPTION This AS4C16M16MD1 is 268,435,456 bits synchronous double data rate Dynamic RAM. Each 67,108,864 bits bank is organized as 8,192 rows by 512 columns by 16 bits, fabricated with Alliance Memory's high performance CMOS technology. This device uses a double data rate architecture to achieve high- speed operation.
AS4C16M16MD1 256Mb MOBILE DDR SDRAM 3.
AS4C16M16MD1 256Mb MOBILE DDR SDRAM 3.1 Signal Descriptions SIGNAL NAME TYPE CK,/CK Input CKE Input /CS Input /RAS,/CAS,/WE LDM,UDM BA0,BA1 Input Input Input Input A [n : 0] DESCRIPTION Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Input and output data is referenced to the crossing of CK and CK (both directions of crossing). Internal clock signals are derived from CK/CK.
AS4C16M16MD1 256Mb MOBILE DDR SDRAM 3.2 Mobile DDR SDRAM Addressing Table Number of banks Bank address pins Auto precharge pin X16 ITEM 256 Mb 4 BA0,BA1 A10/AP A0-A12 A0-A8 7.8 Row addresses Column addresses tREFI(µs) Table 2 — Addressing Table Confidential - 7/56 - Ver.1.1 Oct.
AS4C16M16MD1 256Mb MOBILE DDR SDRAM 4. BLOCK DIAGRAM 4.1 Block Diagram Figure.2 — Block Diagram Confidential - 8/56 - Ver.1.1 Oct.
AS4C16M16MD1 256Mb MOBILE DDR SDRAM 4.2 Simplified State Diagram Figure.3 — State Diagram Confidential - 9/56 - Ver.1.1 Oct.
AS4C16M16MD1 256Mb MOBILE DDR SDRAM 5. FUNCTION DESCRIPTION The LPDDR SDRAM is a high speed CMOS, dynamic random-access memory internally configured as a quad-bank DRAM. These devices contain the following number of bits: 256 Mb has 268,435,456 bits The LPDDR SDRAM uses a double data rate architecture to achieve high speed operation. The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins.
AS4C16M16MD1 256Mb MOBILE DDR SDRAM 5.1.1 Initialization Flow Diagram Figure.4 — Flow Diagram Confidential - 11/56 - Ver.1.1 Oct.
AS4C16M16MD1 256Mb MOBILE DDR SDRAM Figure 5 — Initialization Waveform Sequence Confidential - 12/56 - Ver.1.1 Oct.
AS4C16M16MD1 256Mb MOBILE DDR SDRAM 5.2 Register Definition 5.2.1 Mode Register The Mode Register is used to define the specific mode of operation of the LPDDR SDRAM. This definition includes the definition of a burst length, a burst type, a CAS latency as shown below table. The Mode Register is programmed via the MODE REGISTER SET command (with BA0=0 and BA1=0) and will retain the stored information until it is reprogrammed, the device goes into Deep Power-Down mode, or the device loses power.
AS4C16M16MD1 256Mb MOBILE DDR SDRAM 5.
AS4C16M16MD1 256Mb MOBILE DDR SDRAM Notes: 1. 2. 3. 4. 5. 6. 16-word burst length is optional. For a burst length of two, A1-An selects the two data element block; A0 selects the first access within the block. For a burst length of four, A2-An selects the four data element block; A0-A1 selects the first access within the block. For a burst length of eight, A3-An selects the eight data element block; A0-A2 selects the first access within the block.
AS4C16M16MD1 256Mb MOBILE DDR SDRAM BA1 1 BA0 0 A[n]~A8 Reserved A7 A6 A5 Drive Strength 000b: Full Strength Driver 001b: Half Strength Driver 010b:Quarter Strength Driver 011b:Octant Strength Driver 100b:ThreeQuarters Strength Driver A4 Reserved A3 A2 A1 A0 PASR 000b : All banks 001b : 1/2 array(BA1=0) 010b : ¼ array(BA1=BA0=0) 101b : 1/8 array (BA1 = BA0 = Row Addr MSB = 0) 110b : 1/16 array (BA1=BA0 = Row Addr 2 MSB = 0) 5.2.2.
AS4C16M16MD1 256Mb MOBILE DDR SDRAM 6. COMMANDS All commands (address and control signals) are registered on the positive edge of clock (crossing of CK going high and CK going low). Figure 6 shows basic timing parameters for all commands. Table 5, Table 6 and Table 7 provide a quick reference of available commands. Table 8 and Table 9 provide the current state / next state information. This is followed by a verbal description of each command.
AS4C16M16MD1 256Mb MOBILE DDR SDRAM CKEn-1 CKEn CURRENT STATE COMMANDn ACTIONn NOTES L L Power Down X Maintain Power Down L L Self Refresh X Maintain Self Refresh L L Deep Power Down X Maintain Deep Power Down L H Power Down NOP or DESELECT Exit Power Down 5, 6, 9 L H Self Refresh NOP or DESELECT Exit Self Refresh 5, 7, 10 L H Deep Power Down NOP or DESELECT Exit Deep Power Down 5, 8 H L All Banks Idle NOP or DESELECT Precharge Power Down Entry 5 H L Bank(s) A
AS4C16M16MD1 256Mb MOBILE DDR SDRAM CURRENT STATE Any Idle Row Active Read (Auto precharge Disabled) Write (Auto precharge Disabled) CS RAS CAS WE COMMAND ACTION NOTES H X X X DESELECT NOP or Continue previous operation L H H H No Operation NOP or Continue previous operation L L H H ACTIVE Select and activate row L L L H AUTO REFRESH Auto refresh 10 L L L L MRS Mode register set 10 L H L H READ Select column & start read burst L H L L WRITE Select column
AS4C16M16MD1 256Mb MOBILE DDR SDRAM 10. 11. 12. 13. Accessing Mode Register: Starts with registration of a MODE REGISTER SET command and ends when tMRD has been met. Once tMRD is met, the Mobile DDR SDRAM will be in an ‘all banks idle’ state. Precharging All: Starts with the registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, the bank will be in the idle state. Not bank-specific; requires that all banks are idle and no bursts are in progress. Not bank-specific.
AS4C16M16MD1 256Mb MOBILE DDR SDRAM Notes: 1. The table applies when both CKEn-1 and CKEn are HIGH, and after tXSR or tXP has been met if the previous state was Self Refresh or Power Down. 2. DESELECT and NOP are functionally interchangeable. 3. All states and sequences not shown are illegal or reserved. 4. Current State Definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met.
AS4C16M16MD1 256Mb MOBILE DDR SDRAM 7.OPERATION 7.1. Deselect The DESELECT function (/CS HIGH) prevents new commands from being executed by the Mobile DDR SDRAM. The Mobile DDR SDRAM is effectively deselected. Operations already in progress are not affected. 7.2. No Operation The NO OPERATION (NOP) command is used to instruct the selected DDR SDRAM to perform a NOP (/CS = LOW, / RAS = /CAS = /WE = HIGH). This prevents unwanted commands from being registered during idle or wait states.
AS4C16M16MD1 256Mb MOBILE DDR SDRAM Figure 8 — Mode Register Set Command Figure 9 — Mode Register Set Command Timing 7.4. Active Before any READ or WRITE commands can be issued to a bank in the LPDDR SDRAM, a row in that bank must be opened. This is accomplished by the ACTIVE command (see Figure 10): BA0 and BA1 select the bank, and the address inputs select the row to be activated. More than one bank can be active at any time.
AS4C16M16MD1 256Mb MOBILE DDR SDRAM bank Figure 10 — Active Command Figure 11 — Bank Activation Command Cycle 7.5. Read The READ command (see Figure 12) is used to initiate a burst read access to an active row, with a burst length as set in the Mode Register. BA0 and BA1 select the bank, and the address inputs select the starting column location. The value of A10 determines whether or not Auto Precharge is used.
AS4C16M16MD1 256Mb MOBILE DDR SDRAM Figure 12 — Read Command Figure 13 — Basic Read Timing Parameters Confidential - 25/56 - Ver.1.1 Oct.
AS4C16M16MD1 256Mb MOBILE DDR SDRAM Figure 14 — Read Burst Showing CAS Latency 7.5.1 Read to Read Data from a read burst may be concatenated or truncated by a subsequent READ command. The first data from the new burst follows either the last element of a completed burst or the last desired element of a longer burst that is being truncated.
AS4C16M16MD1 256Mb MOBILE DDR SDRAM Figure 15 — Consecutive Read Bursts Confidential - 27/56 - Ver.1.1 Oct.
AS4C16M16MD1 256Mb MOBILE DDR SDRAM CK CK Command Address READ NOP NOP BA,Col n READ NOP NOP BA,Col b CL=2 DQS DQ DO n DO b CL=3 DQS DO n DQ = Don't Care 1) DO n (or b) =Data Out from column n (or column b) 2) BA,Col n (or b) =Bank A,Column n (or column b) 3) Burst Length=4; 3 subsequent elements of Data Out appear in the programmed order following DO n (or b) 4) Shown with nominal tAC, tDQSCK and tDQSQ Figure 16 — Non-Consecutive Read Bursts Figure 17 — Random Read Bursts Confidential -
AS4C16M16MD1 256Mb MOBILE DDR SDRAM . Figure 18 — Terminating a Read Burst Figure 19 — Read To Write Confidential - 29/56 - Ver.1.1 Oct.
AS4C16M16MD1 256Mb MOBILE DDR SDRAM Figure 20 — Read To Precharge Confidential - 30/56 - Ver.1.1 Oct.
AS4C16M16MD1 256Mb MOBILE DDR SDRAM 6.5.11 Burst Terminate The BURST TERMINATE command is used to truncate read bursts (with Auto Pre-charge disabled). The most recently registered READ command prior to the BURST TERMINATE command will be truncated. Note that the BURST TERMINATE command is not bank specific. This command should not be used to terminate write bursts. Figure 21 — Burst Terminate Command 7.
AS4C16M16MD1 256Mb MOBILE DDR SDRAM Figure 23 — Basic Write Timing Parameters During Write bursts, the first valid data-in element will be registered on the first rising edge of DQS following the WRITE command, and the subsequent data elements will be registered on successive edges of DQS. The Low state of DQS between the WRITE command and the first rising edge is called the write preamble, and the Low state on DQS following the last data-in element is called the write postamble.
AS4C16M16MD1 256Mb MOBILE DDR SDRAM Figure 24 — Write Burst (min. and max. tDQSS) 7.6.1 Write to Write Data for any WRITE burst may be concatenated with or truncated with a subsequent WRITE command. In either case, a continuous flow of input data, can be maintained. The new WRITE command can be issued on any positive edge of the clock following the previous WRITE command.
AS4C16M16MD1 256Mb MOBILE DDR SDRAM Figure 25 — Concatenated Write Bursts Figure 26 — Non-Consecutive Write Bursts Confidential - 34/56 - Ver.1.1 Oct.
AS4C16M16MD1 256Mb MOBILE DDR SDRAM Figure 27 — Random Write Cycles Figure 28 — Non-Interrupting Write to Read Confidential - 35/56 - Ver.1.1 Oct.
AS4C16M16MD1 256Mb MOBILE DDR SDRAM Figure 29 — Interrupting Write to Read Figure 30 — Non-Interrupting Write to Precharge Confidential - 36/56 - Ver.1.1 Oct.
AS4C16M16MD1 256Mb MOBILE DDR SDRAM CK CK Command Address WRITE NOP NOP BA,Col b NOP NOP BA a(or BA,Col n all) tWR tDQSSmax *2 DQS DQ PRE DI b DM *1 *1 *1 1) Dl b = Data in to column b. 2) An interrupted burst of 4, 8 or 16 is shown, 2 data elements are written. 3) tWR is referenced from the positive clock edge after the last desired Data In pair.
AS4C16M16MD1 256Mb MOBILE DDR SDRAM 7.8 Auto Precharge Auto Precharge is a feature which performs the same individual bank precharge function as described above, but without requiring an explicit command. This is accomplished by using A10 (A10 = High), to enable Auto Precharge in conjunction with a specific READ or WRITE command. A precharge of the bank / row that is addressed with the READ or WRITE command is automatically performed upon completion of the read or write burst.
AS4C16M16MD1 256Mb MOBILE DDR SDRAM Partial Array Self Refresh (PASR); they are described in the Extended Mode Register section . Figure 34 — Self Refresh command Figure 35 — Auto Refresh Cycles Back-to-Back Confidential - 39/56 - Ver.1.1 Oct.
AS4C16M16MD1 256Mb MOBILE DDR SDRAM Figure 36 — Self Refresh Entry and Exit 7.12 Power Down Power-down is entered when CKE is registered Low (no accesses can be in progress). If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CK, CK and CKE.
AS4C16M16MD1 256Mb MOBILE DDR SDRAM Figure 37 — Power-Down Entry and Exit Confidential - 41/56 - Ver.1.1 Oct.
AS4C16M16MD1 256Mb MOBILE DDR SDRAM 7.13 Deep Power Down The Deep Power-Down (DPD) mode enables very low standby currents. All internal voltage generators inside the LPDDR SDRAM are stopped and all memory data is lost in this mode. All the information in the Mode Register and the Extended Mode Register is lost. Deep Power-Down is entered using the BURST TERMINATE command (see Figure 21) except that CKE is registered Low.
AS4C16M16MD1 256Mb MOBILE DDR SDRAM 7.14 Clock Stop Stopping a clock during idle periods is an effective method of reducing power consumption.
AS4C16M16MD1 256Mb MOBILE DDR SDRAM 8. ELECTRICAL CHARACTERISTIC 8.1 Absolute Maximum Ratings VALUES PARAMETER SYMBOL UNITS MIN MAX VDD −0.3 2.7 V Voltage on VDDQ relative to VSS VDDQ −0.3 2.7 V Voltage on any pin relative to VSS VIN, VOUT −0.3 2.7 V Tj -30 -40 85 85 °C Storage Temperature TSTG −55 150 °C Short Circuit Output Current IOUT ±50 mA PD 1.0 W Voltage on VDD relative to VSS Operating temperature : Power Dissipation 8.
AS4C16M16MD1 256Mb MOBILE DDR SDRAM 8.3 Electrical Characteristics and AC/DC Operating Conditions All values are recommended operating conditions unless otherwise noted. 8.3.1 Electrical Characteristics and AC/DC Operating Conditions (VDD/VDDQ: 1.7~1.95V) PARAMETER/CONDITION Supply Voltage I/O Supply Voltage SYMBOL MIN MAX UNITS VDD VDDQ 1.70 1.70 1.95 1.95 V V NOTES ADDRESS AND COMMAND INPUTS (A0~An, BA0,BA1,CKE, CS, RAS , CAS , WE ) Input High Voltage VIH 0.8*VDDQ VDDQ + 0.
AS4C16M16MD1 256Mb MOBILE DDR SDRAM 8.4 IDD Specification Parameters and Test Conditions 8.4.
AS4C16M16MD1 256Mb MOBILE DDR SDRAM Notes: 1. IDD specifications are tested after the device is properly initialized. 2. Input slew rate is 1V/ns. 3. Definitions for IDD: LOW is defined as VIN ≤ 0.1 * VDDQ; HIGH is defined as VIN ≥ 0.9 * VDDQ; STABLE is defined as inputs stable at a HIGH or LOW level; SWITCHING is defined as: - Address and command: inputs changing between HIGH and LOW once per two clock cycles; - Data bus inputs: DQ changing between HIGH and LOW once per clock cycle; DM and DQS are STABLE.
AS4C16M16MD1 256Mb MOBILE DDR SDRAM 8.
AS4C16M16MD1 256Mb MOBILE DDR SDRAM PARAMETER PRECHARGE command period ACTIVE bank A to ACTIVE bank B delay WRITE recovery time Auto precharge write recovery + precharge time Internal write to Read command delay Self Refresh exit to next valid command delay Exit power down to next valid command delay CKE min.
AS4C16M16MD1 256Mb MOBILE DDR SDRAM DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers. 12. The only time that the clock frequency is allowed to change is during clock stop, power-down or self-refresh modes. 13.
AS4C16M16MD1 256Mb MOBILE DDR SDRAM Confidential - 51/56 - Ver.1.1 Oct.
AS4C16M16MD1 256Mb MOBILE DDR SDRAM 8.5.2 Output Slew Rate Characteristics PARAMETER Pull-up and Pull-Down Slew Rate for Full Strength Driver Pull-up and Pull-Down Slew Rate for Three-Quarter Strength Driver Pull-up and Pull-Down Slew Rate for Half Strength Driver Output Slew rate Matching ratio (Pull-up to Pull-down) MIN 0.7 0.5 0.3 0.7 MAX 2.5 1.75 1.0 1.4 UNIT V/ns V/ns V/ns - NOTES 1,2 1,2 1,2 3 Notes: 1. Measured with a test load of 20 pF connected to VSSQ. 2.
AS4C16M16MD1 256Mb MOBILE DDR SDRAM 8.5.4 AC Overshoot and Undershoot Definition Figure 40 — AC Overshoot and Undershoot Definition Confidential - 53/56 - Ver.1.1 Oct.
AS4C16M16MD1 256Mb MOBILE DDR SDRAM 9.PACKAGE DIMENSION 60Ball Fine Pitch BGA (8.0x9.0mm) Confidential - 54/56 - Ver.1.1 Oct.
AS4C16M16MD1 256Mb MOBILE DDR SDRAM PART NUMBERING SYSTEM AS4C DRAM Confidential 16M16MD1 16M16=16Mx16 MD1=Mobile DDR1 -6 6=166MHz B B = FBGA - 55/56 - C C=Commercial Extended (-30° C 85° C) N Indicates Pb and Halogen Free Ver.1.1 Oct.
AS4C16M16MD1 256Mb MOBILE DDR SDRAM Alliance Memory, Inc. 511 Taylor Way, San Carlos, CA 94070 Tel: 650-610-6800 Fax: 650-620-9211 www.alliancememory.com Copyright © Alliance Memory All Rights Reserved © Copyright 2007 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies.
