AS4C256M16D3LB-12BIN AS4C256M16D3LB-12BCN Revision History 4Gb AS4C256M16D3LB - 12BIN/BCN 96 ball FBGA PACKAGE Revision Rev 1.0 Rev 1.1 Details Preliminary datasheet Add Industrial part datasheet Date Apr. 2016 Jan. 2017 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1 of 46 - Rev.1.1 Jan.
AS4C256M16D3LB-12BIN AS4C256M16D3LB-12BCN Specifications - - - - - Density : 4G bits Organization : 32M words x 16 bits x 8 banks Package : - 96-ball FBGA - Lead-free (RoHS compliant) and Halogen-free Power supply : VDD, VDDQ = 1.35V (1.283V to 1.45V) - Backward compatible to VDD, VDDQ = 1.5V ± 0.
AS4C256M16D3LB-12BIN AS4C256M16D3LB-12BCN Pin Configurations 96-ball FBGA (x16 configuration) 1 2 3 4 5 6 7 8 A VDDQ DQU5 DQU7 B VSSQ VDD VSS C VDDQ DQU3 DQU1 D VSSQ VDDQ E VSS VSSQ F VDDQ DQL2 DQSL G VSSQ DQL6 DQSL VDD H VREFDQ VDDQ DQL4 DQL7 J NC VSS RAS CK K ODT VDD CAS L NC CS WE M VSS BA0 BA2 N VDD A3 A0 P VSS A5 A2 R VDD A7 A9 T VSS RESET A13 DQU4 VDDQ VSS A DQSU DQU6 VSSQ B DQSU DQU2 VDDQ C DMU DQU0 VSSQ VDD D
AS4C256M16D3LB-12BIN AS4C256M16D3LB-12BCN Signal Pin Description Pin Type Function CK, CK Input Clock : CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK CKE Input Clock Enable : CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers.
AS4C256M16D3LB-12BIN AS4C256M16D3LB-12BCN Pin Type NC Function No Connect: No internal electrical connection is present. VDDQ Supply DQ power supply: 1.35V, 1.283 - 1.45V operational; compatible to 1.5+/- 0.075V operation. VSSQ Supply DQ Ground VDD Supply Power Supply: 1.35V, 1.283 - 1.45V operational; compatible to 1.5+/- 0.075V operation.
AS4C256M16D3LB-12BIN AS4C256M16D3LB-12BCN Simplified State Diagram CKE L Power applied Power on Reset procedure MRS, MPR, write leveling Initialization SRE ZQCL From any state RESET ZQ calibration Self refresh MRS ZQCL/ZQCS SRX REF Idle Refreshing PDE ACT PDX Active powerdown Precharge powerdown Activating PDX CKE L CKE L PDE Bank active WRITE WRITE WRITE AP Writing WRITE READ READ AP READ Reading WRITE AP READ AP WRITE AP Writing READ READ AP PRE, PREA PRE, PREA PRE,
AS4C256M16D3LB-12BIN AS4C256M16D3LB-12BCN Basic Functionality Read and write operation to the DDR3 SDRAM are burst oriented, start at a selected location, and continue for a burst length of four or eight in a programmed sequence. Operation begins with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the Active command are used to select the bank and row to be accessed (BA0-BA2 select the bank; A0-A15 select the row).
AS4C256M16D3LB-12BIN AS4C256M16D3LB-12BCN Ta . Tb Tc . Td . Te . Tf . Tg . Th . Ti . Tj .
AS4C256M16D3LB-12BIN AS4C256M16D3LB-12BCN Mode Register MR0 The Mode Register MR0 stores the data for controlling various operating modes of DDR3 SDRAM. It controls burst length, read burst type, CAS latency, test mode, DLL reset, WR and DLL control for precharge power-down, which include various vendor specific options to make DDR3 SDRAM useful for various applications.
AS4C256M16D3LB-12BIN AS4C256M16D3LB-12BCN Mode Register MR1 The Mode Register MR1 stores the data for enabling or disabling the DLL, output driver strength, RTT_Nom impedance, additive latency, write leveling enable and Qoff. The Mode Register 1 is written by asserting low on CS, RAS, CAS, WE, high on BA0, low on BA1 and BA2, while controlling the states of address pins according to the table below.
AS4C256M16D3LB-12BIN AS4C256M16D3LB-12BCN Mode Register MR2 The Mode Register MR2 stores the data for controlling refresh related features, RTT_WR impedance and CAS write latency (CWL). The Mode Register 2 is written by asserting low on CS, RAS, CAS, WE, high on BA1, low on BA0 and BA2, while controlling the states of address pins according to the table below.
AS4C256M16D3LB-12BIN AS4C256M16D3LB-12BCN Mode Register MR3 The Mode Register MR3 controls Multi Purpose Registers (MPR). The Mode Register 3 is written by asserting low on CS, RAS, CAS, WE, high on BA1 and BA0, and low on BA2 while controlling the states of address pins according to the table below.
AS4C256M16D3LB-12BIN AS4C256M16D3LB-12BCN Burst Type (MR0) [Burst Length and Sequence] Burst length Operation Starting address (A2, A1, A0) Sequential addressing (decimal) Interleave addressing (decimal) 4 (Burst chop) READ 000 0, 1, 2, 3, T, T, T, T 0, 1, 2, 3, T, T, T, T 8 001 1, 2, 3, 0, T, T, T, T 1, 0, 3, 2, T, T, T, T 010 2, 3, 0, 1, T, T, T, T 2, 3, 0, 1, T, T, T, T 011 3, 0, 1, 2, T, T, T, T 3, 2, 1, 0, T, T, T, T 100 4, 5, 6, 7, T, T, T, T 4, 5, 6, 7, T, T, T, T 101 5, 6, 7,
AS4C256M16D3LB-12BIN AS4C256M16D3LB-12BCN Command Truth Table (a) Note 1,2,3,4 apply to the entire Command truth table (b) Note 5 applies to all Read/Write commands.
AS4C256M16D3LB-12BIN AS4C256M16D3LB-12BCN CKE Truth Table (a) Note 1~7 apply to the entire Command truth table (b) CKE low is allowed only if tMRD and tMOD are satisfied CKE Current State 2 Previous Cycle (N-1) 1 Command (N) Current Cycle (N) 3 1 RAS, CAS, WE, CS Action (N) 3 Notes 14, 15 L L X Maintain Power-Down L H DESELECT or NOP Power Down Exit 11, 14 L L X Maintain Self Refresh 15, 16 L H DESELECT or NOP Self Refresh Exit 8, 12, 16 Bank(s) Active H L DESELECT or NOP A
AS4C256M16D3LB-12BIN AS4C256M16D3LB-12BCN Absolute Maximum DC Ratings Symbol Parameter Rating Units Notes VDD Voltage on VDD pin relative to Vss -0.4 V ~ 1.975 V V 1,3 VDDQ Voltage on VDDQ pin relative to Vss -0.4 V ~ 1.975 V V 1,3 VIN, VOUT Voltage on any pin relative to Vss -0.4 V ~ 1.975 V V 1 TSTG Storage Temperature -55 to +100 °C 1,2 NOTE : 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
AS4C256M16D3LB-12BIN AS4C256M16D3LB-12BCN 2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together. 3. VDD and VDDQ rating are determined by operation voltage. AC and DC Input Measurement Levels Single-Ended AC and DC Input Levels for Command and Address(1.35V) Symbol Parameter Min. Max. Units Notes VIHCA (DC90) DC input logic high VREF + 0.090 VDD V 1,5(a) VILCA (DC90) DC input logic low VSS VREF - 0.090 V 1,6(a) VIHCA (AC160) AC input logic high VREF + 0.
AS4C256M16D3LB-12BIN AS4C256M16D3LB-12BCN Symbol Parameter Min. Max. Units Notes VILCA (AC125) AC input logic low - - V 1,2 VREFCA (DC) Reference voltage for ADD, CMD inputs 0.49 * VDD 0.51 * VDD V 3,4 NOTE : 1. For input only pins except /RESET : VREF = VREFCA (DC). 2. See Overshoot and Undershoot Specifications section. 3. The AC peak noise on VREF may not allow VREF to deviate from VREFCA (DC) by more than ±1% VDD (for reference : approx. ±15 mV). 4. For reference : approx.
AS4C256M16D3LB-12BIN AS4C256M16D3LB-12BCN Single-Ended AC and DC Input Levels for DQ and DM(1.5V) Symbol Parameter Min. Max. Units Notes VIHDQ (DC100) DC input logic high VREF + 0.100 VDD V 1 VILDQ (DC100) DC input logic low VSS VREF - 0.100 V 1 VIHDQ (AC175) AC input logic high - - V 1,2 VILDQ (AC175) AC input logic low - - V 1,2 VIHDQ (AC150) AC input logic high VREF + 0.150 - V 1,2 VILDQ (AC150) AC input logic low - VREF - 0.
AS4C256M16D3LB-12BIN AS4C256M16D3LB-12BCN VREF Tolerances The dc-tolerance limits and ac-noise limits for the reference voltages VREFCA and VREFDQ are illustrate in figure VREF(DC) tolerance and VREF AC-Noise limits. It shows a valid reference voltage VREF(t) as a function of time. (VREF stands for VREFCA and VREFDQ likewise). VREF(DC) is the linear average of VREF(t) over a very long period of time (e.g. 1 sec).
AS4C256M16D3LB-12BIN AS4C256M16D3LB-12BCN AC and DC Logic Input Levels for Differential Signals Differential signals definition tDVAC Differential Input Voltage (i.e. DQS-DQS, CK-CK) VIH.DIFF.AC.MIN VIH.DIFF.MIN 0.0 half cycle VIL.DIFF.MAX VIL.DIFF.AC.MAX tDVAC time Definition of differential ac-swing and "time above ac level" tDVAC Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS) Differential AC and DC Input Levels(1.35V) Symbol Parameter Min. Max.
AS4C256M16D3LB-12BIN AS4C256M16D3LB-12BCN NOTE : 1. Used to define a differential signal slew-rate. 2. for CK - CK use VIH/VIL(AC) of address/command and VREFCA; for strobes (DQS, DQS) use VIH/VIL(AC) of DQs and VREFDQ; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here. 3.
AS4C256M16D3LB-12BIN AS4C256M16D3LB-12BCN Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS(1.5V) Slew Rate [V/ns] tDVAC [ps] @ |VIH/Ldiff(AC)| = 350mV tDVAC [ps] @ |VIH/Ldiff(AC)| = 300mV Min. Max. Min. Max. > 4.0 75 - 175 - 4.0 57 - 170 - 3.0 50 - 167 - 2.0 38 - 163 - 1.8 34 - 162 - 1.6 29 - 161 - 1.4 22 - 159 - 1.2 13 - 155 - 1.0 0 - 150 - < 1.0 0 - 150 - NOTE:1.
AS4C256M16D3LB-12BIN AS4C256M16D3LB-12BCN VDD or VDDQ VSEH min VSEH VDD/2 or VDDQ/2 CK or DQS VSEL max VSEL VSS or VSSQ time Single-ended requirement for differential signals Note that while Address/command and DQ signal requirements are with respect to VREF, the single-ended components of differential signals have a requirement with respect to VDD/2; this is nominally the same. The transition of single-ended signals through the AC-levels is used to measure setup time.
AS4C256M16D3LB-12BIN AS4C256M16D3LB-12BCN To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (CK, CK and DQS, DQS) must meet the requirements in below table. The differential input cross point voltage VIX is measured from the actual cross point of true and complement signal to the mid level between of VDD and VSS.
AS4C256M16D3LB-12BIN AS4C256M16D3LB-12BCN Differential input slew rate definition Measured Description Defined by From To Differential input slew rate for rising edge ( CK-CK and DQS-DQS ) VILdiff (max) VIHdiff (min) VIHdiff (min) - VILdiff (max) Delta TRdiff Differential input slew rate for falling edge ( CK-CK and DQS-DQS ) VIHdiff (min) VILdiff (max) VIHdiff (min) - VILdiff (max) Delta TFdiff NOTE : The differential signal (i.e. CK - CK and DQS - DQS) must be linear between these thresholds.
AS4C256M16D3LB-12BIN AS4C256M16D3LB-12BCN AC and DC Output Measurement Levels Single-ended AC & DC Output Levels DDR3L-1600 Parameter Symbol Units Notes VOH(DC) DC output high measurement level (for IV curve linearity) 0.8 x VDDQ V VOM(DC) DC output mid measurement level (for IV curve linearity) 0.5 x VDDQ V VOL(DC) DC output low measurement level (for IV curve linearity) 0.2 x VDDQ V VOH(AC) AC output high measurement level (for output SR) VTT + 0.
AS4C256M16D3LB-12BIN AS4C256M16D3LB-12BCN Parameter DDR3L-1600 Symbol Voltage Single ended output SRQse slew rate Units Min Max 1.35V 1.75 5(1) V/ns 1.5V 2.5 5 V/ns Description : SR : Slew Rate Q : Query Output (like in DQ, which stands for Data-in, Query-Output) se : Single-ended Signals For Ron = RZQ/7 setting NOTE : (1) In two cased, a maximum slew rate of 6V/ns applies for a single DQ signal within a byte lane.
AS4C256M16D3LB-12BIN AS4C256M16D3LB-12BCN Description : SR : Slew Rate Q : Query Output (like in DQ, which stands for Data-in, Query-Output) diff : Differential Signals For Ron = RZQ/7 setting Reference Load for AC Timing and Output Slew Rate Figure represents the effective reference load of 25 ohms used in defining the relevant AC timing parameters of the device as well as output slew rate measurements.
AS4C256M16D3LB-12BIN AS4C256M16D3LB-12BCN Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications Specification Parameter DDR3L-1600 Unit Maximum peak amplitude allowed for overshoot area 0.4V V Maximum peak amplitude allowed for undershoot area 0.4V V Maximum overshoot area above VDD 0.13V-ns V-ns Maximum undershoot area below VSS 0.13V-ns V-ns Clock, Data, Strobe, Mask Overshoot and Undershoot Definition Confidential - 30 of 46 - Rev.1.1 Jan.
AS4C256M16D3LB-12BIN AS4C256M16D3LB-12BCN IDD Specification Conditions Symbol IDD max.
AS4C256M16D3LB-12BIN AS4C256M16D3LB-12BCN Conditions Symbol IDD max. Unit IDD3N 32 mA Operating Burst Read Current; CKE: High; External clock: On; tCK, CL: see timing used table; BL: 8; AL: 0; CS: High between RD; Command, Address: partially toggling; Data IO: seamless read data burst with different data between one burst and the next one; DM: stable at 0; Bank Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,...
AS4C256M16D3LB-12BIN AS4C256M16D3LB-12BCN RTT_Wr enable: set MR2 A[10,9] = 10B 3) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12=1B for Fast Exit 4) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature 5) Self-Refresh Temperature Range (SRT): set MR2 A7=0B for normal or 1B for extended temperature range 6) Refer to DRAM supplier data sheet and/or DIMM SPD to determine if optional features or requirements are supported by DDR3 SDRAM 7) Read Burst type : Nibble Seque
AS4C256M16D3LB-12BIN AS4C256M16D3LB-12BCN Input/Output Capacitance Parameter Symbol DDR3L-1600 Max Min Units NOTE 1.35V Input/output capacitance (DQ, DM, DQS, DQS, TDQS, TDQS) CIO 1.2 2.3 pF 1,2,3 Input capacitance (CK and CK) CCK 0.8 1.4 pF 2,3 CDCK 0 0.15 pF 2,3,4 CI 0.75 1.3 pF 2,3,6 CDDQS 0 0.15 pF 2,3,5 CDI_CTRL -0.4 0.2 pF 2,3,7,8 CDI_ADD_CMD -0.4 0.4 pF 2,3,9,10 Input/output capacitance delta (DQ, DM, DQS, DQS, TDQS, TDQS) CDIO -0.5 0.
AS4C256M16D3LB-12BIN AS4C256M16D3LB-12BCN NOTE : 1. Although the DM pin has different functions, the loading matches DQ and DQS 2. This parameter is not subject to production test. It is verified by design and characterization. The capacitance is measured according to JEP147("PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER( VNA)") with VDD, VDDQ, VSS, VSSQ applied and all other pins floating (except the pin under test, CKE, RESET and ODT as necessary). VDD=VDDQ=1.
AS4C256M16D3LB-12BIN AS4C256M16D3LB-12BCN DDR3L-1600 Speed Bins Speed Bin - 12 (DDR3L-1600) CL-nRCD-nRP 11-11-11 Parameter Unit Notes 20 ns 9 13.75 (13.125) - ns 9 tRP 13.75 (13.125) - ns 9 tRC 48.75 (48.125) - ns 9 Symbol Min Max tAA 13.75 (13.125) tRCD Precharge command period Active to active/auto-refresh command time Internal read command to first data Active to read or write delay time tRAS 35 9 * tREFI ns 8 CWL = 5 tCK(avg) 3.0 3.
AS4C256M16D3LB-12BIN AS4C256M16D3LB-12BCN Speed Bin Table Notes NOTE : 1. The CL setting and CWL setting result in tCK(avg) Min and tCK(avg) Max requirements. When making a selection of tCK(avg), both need to be fulfilled: Requirements from CL setting as well as requirements from CWL setting. 2. tCK(avg) Min limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL all possible intermediate frequencies may not be guaranteed.
AS4C256M16D3LB-12BIN AS4C256M16D3LB-12BCN AC Characteristics - 12 (DDR3L-1600) Parameter Symbol Max Min Unit Note Average clock cycle time tCK(avg) Minimum clock cycle time (DLL-off mode) tCK (DLL-off) 8 - ns Average CK high level width tCH(avg) 0.47 0.53 tCK(avg) Average CK low level width tCL(avg) 0.47 0.53 tCK(avg) 7.
AS4C256M16D3LB-12BIN AS4C256M16D3LB-12BCN - 12 (DDR3L-1600) Parameter DQ and DM input setup time (VIH/VIL (AC) levels) Symbol Min Max Unit Note - ps 17 1.35V tDS(base) AC135 25 1.
AS4C256M16D3LB-12BIN AS4C256M16D3LB-12BCN - 12 (DDR3L-1600) Parameter Multi-purpose register recovery time Internal write to read command delay Internal read to precharge command delay Symbol Min Max Unit Note tMPRR 1 - nCK 22 7.5 - ns 18 4 - nCK 18 7.
AS4C256M16D3LB-12BIN AS4C256M16D3LB-12BCN - 12 (DDR3L-1600) Parameter Symbol Timing of WR command to Power-down entry (BL8OTF, BL8MRS, BL4OTF) tWRPDEN (min) Timing of WR command to Power-down entry (BC4MRS) tWRPDEN (min) Unit Note WL + 4 + [tWR/tCK(avg)] nCK 9 WL + 2 + [tWR/tCK(avg)] nCK 9 nCK 10 nCK 10 nCK 20,21 7 Min Max Timing of WRA command to Power-down tWRAPDEN entry (BL8OTF, BL8MRS, BL4OTF) WL+4 +WR+1 - Timing of WRA command to Power-down tWRAPDEN entry (BC4MRS) WL+2 +WR+1
AS4C256M16D3LB-12BIN AS4C256M16D3LB-12BCN - 12 (DDR3L-1600) Parameter Symbol Min Max Unit Cycle to cycle period jitter tJIT(cc) - 140 ps Cycle to cycle period jitter during DLL locking period tJIT(cc,lck) - 120 ps Cumulative error across 2 cycles tERR(2per) -103 103 ps Cumulative error across 3 cycles tERR(3per) -122 122 ps Cumulative error across 4 cycles tERR(4per) -136 136 ps Cumulative error across 5 cycles tERR(5per) -147 147 ps Cumulative error across 6 cycles tERR(
AS4C256M16D3LB-12BIN AS4C256M16D3LB-12BCN Notes for AC Electrical Characteristics NOTE : 1. Actual value dependant upon measurement level definitions which are TBD. 2. Commands requiring a locked DLL are: READ (and READA) and synchronous ODT commands. 3. The max values are system dependent. 4. WR as programmed in mode register. 5. Value must be rounded-up to next higher integer value. 6. There is no maximum cycle time limit besides the need to satisfy the refresh interval, tREFI. 7. ODT turn on time (min.
AS4C256M16D3LB-12BIN AS4C256M16D3LB-12BCN derating to accommodate for the lower alternate threshold of 150 mV and another 25 ps to account for the earlier reference point [(175 mv - 150 mV) / 1 V/ns]. 25. Pulse width of a input signal is defined as the width between the first crossing of VREF(DC) and the consecutive crossing of VREF(DC). 26. tDQSL describes the instantaneous differential input low pulse width on DQS - DQS, as measured from one falling edge to the next consecutive rising edge. 27.
AS4C256M16D3LB-12BIN AS4C256M16D3LB-12BCN Package Diagram (x16) 96-Ball Fine Pitch Ball Grid Array Outline 24/51 Confidential - 45 of 46 - 24/61 24/71 Rev.1.1 Jan.
AS4C256M16D3LB-12BIN AS4C256M16D3LB-12BCN PART NUMBERING SYSTEM AS4C 256M16D3LB DRAM 256M16=256Mx16 D3L=LPDDR3 B=B die 12 B 12=800MHz B = FBGA C/I C=Commercial (0°C~+95°C) I=Industrial (-40°C~+95°C) N Indicates Pb and Halogen Free Alliance Memory, Inc. 511 Taylor Way, San Carlos, CA 94070 Tel: 650-610-6800 Fax: 650-620-9211 www.alliancememory.com Copyright © Alliance Memory All Rights Reserved © Copyright 2007 Alliance Memory, Inc. All rights reserved.
