AS4C32M16D1A-C&I Revision History Revision Rev 1.0 Details Preliminary datasheet Date March 2015 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice. 0 Rev. 1.0 Mar.
AS4C32M16D1A-C&I 32M x 16 bit DDR Synchronous DRAM (SDRAM) Advanced (Rev. 1.0, Mar. /2015) Features Fast clock rate: 200MHz Differential Clock CK & CK Bi-directional DQS DLL enable/disable by EMRS Fully synchronous operation Internal pipeline architecture Four internal banks, 8M x 16-bit for each bank Programmable Mode and Extended Mode registers - CAS Latency: 2, 2.
AS4C32M16D1A-C&I Overview The 512Mb DDR SDRAM is a high-speed CMOS double data rate synchronous DRAM containing 512 Mbits. It is internally configured as a quad 8M x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CK). Data outputs occur at both rising edges of CK and CK . Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence.
AS4C32M16D1A-C&I Figure 1.
AS4C32M16D1A-C&I Figure 2.
AS4C32M16D1A-C&I Pin Descriptions Table 2. Pin Details Symbol Type Description CK, CK Input Differential Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK . Input and output data is referenced to the crossing of CK and CK (both directions of the crossing) CKE Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CK signal.
AS4C32M16D1A-C&I VSS Supply Ground VDDQ Supply DQ Power: 2.5V ± 0.2V . Provide isolated power to DQs for improved noise immunity. VSSQ Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity. VREF Supply Reference Voltage for Inputs: +0.5*VDDQ NC - No Connect: These pins should be left unconnected. 2 Rev. 1.0 Mar.
AS4C32M16D1A-C&I Operation Mode Table 3 shows the truth table for the operation commands. Table 3.
AS4C32M16D1A-C&I Mode Register Set (MRS) The Mode Register stores the data for controlling various operating modes of a DDR SDRAM. It programs CAS Latency, Burst Type, and Burst Length to make the DDR SDRAM useful for a variety of applications. The default value of the Mode Register is not defined; therefore the Mode Register must be written by the user. Values stored in the register will be retained until the register is reprogrammed.
AS4C32M16D1A-C&I Addressing Mode Select Field (A3) The Addressing Mode can be one of two modes, either Interleave Mode or Sequential Mode. Both Sequential Mode and Interleave Mode support burst length of 2, 4 and 8. Table 6. Addressing Mode A3 Addressing Mode 0 Sequential 1 Interleave Burst Definition, Addressing Sequence of Sequential and Interleave Mode Table 7.
AS4C32M16D1A-C&I ( BA0, BA1) Table 10. MRS/EMRS BA1 BA0 A12 ~ A0 RFU 0 MRS Cycle RFU 1 Extended Functions (EMRS) Extended Mode Register Set (EMRS) The Extended Mode Register Set stores the data for enabling or disabling DLL and selecting output driver strength. The default value of the extended mode register is not defined, therefore must be written after power up for proper operation.
AS4C32M16D1A-C&I Table 12. Absolute Maximum Rating Symbol Item VIN, VOUT Input, Output Voltage VDD, VDDQ Power Supply Voltage TA Ambient Temperature TSTG Storage Temperature TSOLDER PD Values Unit - 0.5~ VDDQ + 0.5 V - 1~3.6 V 0~70 °C -40~85 °C - 55~150 °C 260 °C 1 W Commercial Industrial Soldering Temperature Power Dissipation IOS Short Circuit Output Current 50 mA Note1: Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
AS4C32M16D1A-C&I Table 15. D.C. Characteristics (VDD = 2.5V 0.2V, TA = -40~85 C) Parameter & Test Condition OPERATING CURRENT: One bank; Active-Precharge; tRC=tRC(min); tCK=tCK(min); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles.
AS4C32M16D1A-C&I Table 16. Electrical Characteristics and Recommended A.C.Operating Condition (VDD = 2.5V ± 0.2V, TA = -40~85 C) Symbol -5 Parameter CL = 2 CL = 2.5 CL = 3 Min. 7.5 6 5 0.45 0.45 tCLMIN or tCHMIN Max. 12 12 12 0.55 0.55 - Unit Note ns ns ns tCK tCK ns 2 tCK Clock cycle time tCH tCL tHP Clock high level width Clock low level width Clock half period tHZ Data-out-high impedance time from CK, CK - 0.7 ns 3 tLZ Data-out-low impedance time from CK, CK -0.7 0.
AS4C32M16D1A-C&I Table 17. Recommended A.C. Operating Conditions (VDD = 2.5V ± 0.2V, TA = -40~85 C) Symbol Parameter Min. Max. Unit VIH (AC) Input High Voltage (AC) VREF + 0.31 - V VIL (AC) Input Low Voltage (AC) - VREF – 0.31 V 0.7 VDDQ + 0.6 V 0.5*VDDQ-0.2 0.5*VDDQ+0.2 V VID (AC) Input Different Voltage, CK and CK inputs VIX (AC) Input Crossing Point Voltage, CK and CK inputs Note: 1) Enables on-chip refresh and address counters.
AS4C32M16D1A-C&I Figure 3. SSTL_2 A.C. Test Load 0.5 * VDDQ 50Ω DQ, DQS Z0=50Ω 30pF 10) Power up Sequence Power up must be performed in the following sequence. 1) 2) 3) 4) 5) 6) 7) 8) Apply power to VDD before or at the same time as VDDQ, VTT and VREF when all input signals are held "NOP" state and maintain CKE “LOW”. Start clock and maintain stable condition for minimum 200s. Issue a “NOP” command and keep CKE “HIGH” Issue a “Precharge All” command. Issue EMRS – enable DLL. Issue MRS – reset DLL.
AS4C32M16D1A-C&I Timing Waveforms Figure 4. Activating a Specific Row in a Specific Bank CK CK CKE HIGH CS RAS CAS WE Address RA BA0,1 BA RA=Row Address BA=Bank Address Don’t Care 12 Rev. 1.0 Mar.
AS4C32M16D1A-C&I Figure 5. tRCD and tRRD Definition CK CK COMMAND ACT Address Row Row Col BA0,BA1 Bank A Bank B Bank B NOP NOP ACT tRRD NOP NOP RD/WR NOP tRCD Don’t Care Figure 6. READ Command CK CK CKE HIGH CS RAS CAS WE A0 - A9 CA EN AP A10 DIS AP BA0,1 BA CA=Column Address BA=Bank Address EN AP=Enable Autoprecharge DIS AP=Disable Autoprecharge Don’t Care 13 Rev. 1.0 Mar.
AS4C32M16D1A-C&I Figure 7. Read Burst Required CAS Latencies (CL=2) CK CK COMMAND READ ADDRESS Bank A, Col n NOP NOP NOP NOP NOP CL=2 DQS DO n DQ DO n=Data Out from column n Burst Length=4 3 subsequent elements of Data Out appear in the programmed order following DO n Don’t Care Read Burst Required CAS Latencies (CL=2.5) CK CK COMMAND READ ADDRESS Bank A, Col n NOP NOP NOP NOP NOP CL=2.
AS4C32M16D1A-C&I Read Burst Required CAS Latencies (CL=3) CK CK COMMAND READ ADDRESS Bank A, Col n NOP NOP NOP NOP NOP CL=3 DQS DO n DQ DO n=Data Out from column n Burst Length=4 3 subsequent elements of Data Out appear in the programmed order following DO n Don’t Care 15 Rev. 1.0 Mar.
AS4C32M16D1A-C&I Figure 8.
AS4C32M16D1A-C&I Consecutive Read Bursts Required CAS Latencies (CL=2.5) CK CK COMMAND ADDRESS READ NOP READ NOP NOP NOP Bank, Col o Bank, Col n CL=2.
AS4C32M16D1A-C&I Consecutive Read Bursts Required CAS Latencies (CL=3) CK CK COMMAND ADDRESS READ NOP Bank, Col n READ NOP NOP NOP Bank, Col o CL=3 DQS DO n DQ DO o DO n (or o)=Data Out from column n (or column o) Burst Length=4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first) 3 subsequent elements of Data Out appear in the programmed order following DO n 3 (or 7) subsequent elements of Data Out appear in the programmed order following DO o Read commands sh
AS4C32M16D1A-C&I Figure 9. Non-Consecutive Read Bursts Required CAS Latencies (CL=2) CK CK COMMAND ADDRESS READ NOP NOP READ NOP NOP Bank, Col o Bank, Col n CL=2 DQS DO n DQ DO o DO n (or o)=Data Out from column n (or column o) Burst Length=4 3 subsequent elements of Data Out appear in the programmed order following DO n (and following DO o) Don’t Care Non-Consecutive Read Bursts Required CAS Latencies (CL=2.
AS4C32M16D1A-C&I Non-Consecutive Read Bursts Required CAS Latencies (CL=3) CK CK COMMAND ADDRESS READ NOP NOP READ NOP NOP NOP Bank, Col o Bank, Col n CL=3 DQS DO n DQ DO o DO n (or o)=Data Out from column n (or column o) Burst Length=4 3 subsequent elements of Data Out appear in the programmed order following DO n (and following DO o) Don’t Care 20 Rev. 1.0 Mar.
AS4C32M16D1A-C&I Figure 10. Random Read Accesses Required CAS Latencies (CL=2) CK CK COMMAND ADDRESS READ READ READ READ Bank, Col n Bank, Col o Bank, Col p Bank, Col q NOP NOP CL=2 DQS DO n' DO n DQ DO o' DO o DO p DO p' DO q DO n, etc. =Data Out from column n, etc. n', etc. =the next Data Out following DO n, etc. according to the programmed burst order Burst Length=2,4 or 8 in cases shown.
AS4C32M16D1A-C&I Random Read Accesses Required CAS Latencies (CL=3) CK CK COMMAND ADDRESS READ READ READ READ Bank, Col n Bank, Col o Bank, Col p Bank, Col q NOP NOP CL=3 DQS DO n DQ DO n' DO o DO o' DO p DO n, etc. =Data Out from column n, etc. n', etc. =the next Data Out following DO n, etc. according to the programmed burst order Burst Length=2,4 or 8 in cases shown. If burst of 4 or 8, the burst is interrupted Reads are to active rows in any banks Don’t Care 22 Rev. 1.0 Mar.
AS4C32M16D1A-C&I Figure 11. Terminating a Read Burst Required CAS Latencies (CL=2) CK CK COMMAND READ ADDRESS Bank A, Col n NOP BST NOP NOP NOP CL=2 DQS DO n DQ DO n = Data Out from column n Cases shown are bursts of 8 terminated after 4 data elements 3 subsequent elements of Data Out appear in the programmed order following DO n Don’t Care Terminating a Read Burst Required CAS Latencies (CL=2.5) CK CK COMMAND READ ADDRESS Bank A, Col n NOP BST NOP NOP NOP CL=2.
AS4C32M16D1A-C&I Terminating a Read Burst Required CAS Latencies (CL=3) CK CK COMMAND READ ADDRESS Bank A, Col n NOP BST NOP NOP NOP CL=3 DQS DO n DQ DO n = Data Out from column n Cases shown are bursts of 8 terminated after 4 data elements 3 subsequent elements of Data Out appear in the programmed order following DO n Don’t Care 24 Rev. 1.0 Mar.
AS4C32M16D1A-C&I Figure 12.
AS4C32M16D1A-C&I Read to Write Required CAS Latencies (CL=2.5) CK CK COMMAND ADDRESS READ BST NOP NOP NOP WRITE Bank, Col o Bank, Col n CL=2.
AS4C32M16D1A-C&I Read to Write Required CAS Latencies (CL=3) CK CK COMMAND ADDRESS READ BST NOP NOP NOP WRITE Bank, Col o Bank, Col n tDQSS min CL=3 DQS DO n DQ DI o DM DO n (or o)= Data Out from column n (or column o) Burst Length= 4 in the cases shown (applies for bursts of 8 as well; if burst length is 2, the BST command shown can be NOP) 1 subsequent element of Data Out appears in the programmed order following DO n Data in elements are applied following DI o in the programmed order Don’
AS4C32M16D1A-C&I Figure 13.
AS4C32M16D1A-C&I Read to Precharge Required CAS Latencies (CL=2.5) CK CK COMMAND READ NOP PRE NOP NOP ACT tRP ADDRESS Bank A, Col n Bank (a or all) Bank A, Row CL=2.
AS4C32M16D1A-C&I Read to Precharge Required CAS Latencies (CL=3) CK CK COMMAND READ NOP PRE NOP NOP ACT tRP ADDRESS Bank A, Col n Bank (a or all) Bank A, Row CL=3 DQS DO n DQ DO n = Data Out from column n Cases shown are either uninterrupted bursts of 4, or interrupted bursts of 8 3 subsequent elements of Data Out appear in the programmed order following DO n Precharge may be applied at (BL/2) tCK after the READ command Note that Precharge may not be issued before tRAS ns after the ACTIVE com
AS4C32M16D1A-C&I Figure 14. Write Command CK CK CKE HIGH CS RAS CAS WE A0 - A9 CA EN AP A10 DIS AP BA0,1 BA CA=Column Address BA=Bank Address EN AP=Enable Autoprecharge DIS AP=Disable Autoprecharge Don’t Care 31 Rev. 1.0 Mar.
AS4C32M16D1A-C&I Figure 15. Write Max DQSS T0 T1 T2 T3 T4 T5 T6 T7 CK CK COMMAND WRITE ADDRESS Bank A, Col n NOP NOP NOP tDQSS max DQS DQ DI n DM DI n = Data In for column n 3 subsequent elements of Data In are applied in the programmed order following DI n A non-interrupted burst of 4 is shown A10 is LOW with the WRITE command (AUTO PRECHARGE disabled) Don’t Care 32 Rev. 1.0 Mar.
AS4C32M16D1A-C&I Figure 16. Write Min DQSS T0 T1 T2 T3 T4 T5 T6 CK CK COMMAND ADDRESS NOP WRITE NOP NOP Bank A, Col n tDQSS min DQS DQ DI n DM DI n = Data In for column n 3 subsequent elements of Data In are applied in the programmed order following DI n A non-interrupted burst of 4 is shown A10 is LOW with the WRITE command (AUTO PRECHARGE disabled) Don’t Care 33 Rev. 1.0 Mar.
AS4C32M16D1A-C&I Figure 17.
AS4C32M16D1A-C&I Figure 18. Write to Write Max tDQSS T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 CK CK COMMAND ADDRESS WRITE NOP WRITE NOP NOP NOP Bank , Col o Bank , Col n tDQSS (max) DQS DQ DI n DI o DM DI n , etc. = Data In for column n,etc. 3 subsequent elements of Data In are applied in the programmed order following DI n 3 subsequent elements of Data In are applied in the programmed order following DI o Non-interrupted bursts of 4 are shown DM= UDM & LDM Don’t Care 35 Rev. 1.
AS4C32M16D1A-C&I Figure 19. Write to Write Max tDQSS, Non Consecutive T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 CK CK COMMAND ADDRESS WRITE NOP NOP Bank Col n WRITE NOP NOP Bank Col o tDQSS (max) DQS DQ DI n DI o DM DI n, etc. = Data In for column n, etc.
AS4C32M16D1A-C&I Figure 20. Random Write Cycles Max tDQSS T0 T1 T2 T4 T3 T5 T6 T8 T7 T9 CK CK COMMAND ADDRESS WRITE WRITE WRITE WRITE WRITE Bank Col n Bank Col o Bank Col p Bank Col q Bank Col r tDQSS (max) DQS DQ DI n DI n' DI o DI o' DI p DI p' DI q DI q' DM DI n, etc. = Data In for column n, etc. n', etc. = the next Data In following DI n, etc.
AS4C32M16D1A-C&I Figure 21. Write to Read Max tDQSS Non Interrupting T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CK CK COMMAND WRITE NOP NOP NOP READ NOP NOP tWTR ADDRESS Bank Col o Bank Col n CL=3 tDQSS (max) DQS DI n DQ DM DI n, etc. = Data In for column n, etc.
AS4C32M16D1A-C&I Figure 22. Write to Read Max tDQSS Interrupting T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CK CK COMMAND WRITE NOP NOP NOP READ NOP tWTR ADDRESS Bank Col o Bank Col n CL=3 tDQSS (max) DQS DI n DQ DM DI n, etc. = Data In for column n, etc.
AS4C32M16D1A-C&I Figure 23.
AS4C32M16D1A-C&I Figure 24.
AS4C32M16D1A-C&I Figure 25.
AS4C32M16D1A-C&I Figure 26.
AS4C32M16D1A-C&I Figure 27. Precharge Command CK CK CKE HIGH CS RAS CAS WE A0-A9, A11,A12 ALL BANKS A10 ONE BANK BA0,1 BA BA= Bank Address (if A10 is LOW, otherwise don't care) Don’t Care 44 Rev. 1.0 Mar.
AS4C32M16D1A-C&I Figure 28. Power-Down T0 T1 T2 T3 T4 Tn Tn+3 Tn+4 Tn+5 Tn+6 Tn+1 Tn+2 CK CK tIS tIS CKE COMMAND NOP NOP VALID Exit power-down mode Enter power-down mode No column access in progress VALID Don’t Care Figure 29.
AS4C32M16D1A-C&I Figure 30. Data input (Write) Timing tDQSH tDQSL DQS tDS DI n DQ tDH tDS DM tDH DI n = Data In for column n Burst Length = 4 in the case shown 3 subsequent elements of Data In are applied in the programmed order following DI n Don’t Care Figure 31. Data Output (Read) Timing tCH tCL CK CK DQS DQ tDQSQ tDQSQ max max tQH tQH Burst Length = 4 in the case shown 46 Rev. 1.0 Mar.
AS4C32M16D1A-C&I Figure 32.
AS4C32M16D1A-C&I Figure 33. Power Down Mode tCK tCH tCL CK CK tIS tIH tIS tIS CKE tIS tIH COMMAND VALID* NOP NOP VALID tIS tIH ADDR VALID VALID DQS DQ DM Enter power-down mode Exit power-down mode No column accesses are allowed to be in progress at the time Power-Down is entered *=If this command is a PRECHARGE ALL (or if the device is already in the idle state) then the Power-Down mode shown is Precharge Power Down.
AS4C32M16D1A-C&I Figure 34. Auto Refresh Mode tCK tCH tCL CK CK tIS tIH CKE VALID VALID tIS tIH COMMAND NOP PRE NOP NOP AR NOP AR NOP NOP ACT A0-A9 RA A11,A12 RA ALL BANKS RA A10 ONE BANKS tIS tIH BA0,BA1 BA *Bank(s) DQS DQ DM tRP tRFC tRFC * = “Don't Care”, if A10 is HIGH at this point; A10 must be HIGH if more than one bank is active (i.e.
AS4C32M16D1A-C&I Figure 35.
AS4C32M16D1A-C&I Figure 36.
AS4C32M16D1A-C&I Figure 37.
AS4C32M16D1A-C&I Figure 38.
AS4C32M16D1A-C&I Figure 39.
AS4C32M16D1A-C&I Figure 40.
AS4C32M16D1A-C&I Figure 41.
AS4C32M16D1A-C&I Figure 42.
AS4C32M16D1A-C&I Figure 43. 66 Pin TSOP II Package Outline Drawing Information Units: mm D D C A2 L E HE L1 C A θ A1 b e S F (TYP) Symbol A A1 A2 b e C D E HE L L1 F θ S D y Dimension in mm Min Nom Max --0.05 0.9 0.22 --0.095 22.09 10.03 11.56 0.40 ----0° ----- ----1.0 --0.65 0.125 22.22 10.16 11.76 0.5 0.8 0.25 --0.71 --- 1.2 0.2 1.1 0.45 --0.21 22.35 10.29 11.96 0.6 ----8° --0.10 Dimension in inch Min Nom Max --0.002 0.035 0.009 --0.004 0.87 0.395 0.455 0.016 ----0° ----- 58 ----0.
AS4C32M16D1A-C&I PART NUMBERING SYSTEM AS4C DRAM 32M16D1A 32M16=32Mx16bit D1A=DDR1（A version） 5 T 5=200MHz T = TSOP II C/I C=Commercial (0° C ～ 70° C) I=Industrial (-40° C ～ 85° C) N Indicates Pb and Halogen Free Alliance Memory, Inc. 511 Taylor Way, San Carlos, CA 94070 Tel: 650-610-6800 Fax: 650-620-9211 www.alliancememory.com Copyright © Alliance Memory All Rights Reserved © Copyright 2007 Alliance Memory, Inc. All rights reserved.
