AS4C32M16D2A-25BCN 32M x 16 bit DDR2 Synchronous DRAM (SDRAM) Advanced (Rev. 1.4, Jun. /2014) Features Overview • JEDEC Standard Compliant • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Power supplies: VDD & VDDQ = +1.8V ± 0.
AS4C32M16D2A-25BCN Table 2. Speed Grade Information Speed Grade Clock Frequency CAS Latency tRCD (ns) tRP (ns) AS4C32M16D2A-25BCN 400MHz 5 12.5 12.5 Figure 1. Ball Assignment (FBGA Top View) 1 2 3 7 8 9 A VDD NC VSS VSSQ UDQS# VDDQ B DQ14 VSSQ UDM UDQS.
AS4C32M16D2A-25BCN Figure 2.
AS4C32M16D2A-25BCN Figure 3.
AS4C32M16D2A-25BCN Ball Descriptions Table 3. Ball Descriptions Symbol Type Description CK, CK# Input Differential Clock: CK, CK# are driven by the system clock. All SDRAM input signals are sampled on the crossing of positive edge of CK and negative edge of CK#. Output (Read) data is referenced to the crossings of CK and CK# (both directions of crossing). CKE Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CK signal.
AS4C32M16D2A-25BCN On Die Termination: ODT enables internal termination resistance. It is applied to each DQ, LDQS/LDQS#, UDQS/UDQS#, LDM, and UDM signal. The ODT pin is ignored if the EMR (1) is programmed to disable ODT. ODT Input VDD Supply Power Supply: +1.8V ±0.1V VSS Supply Ground VDDL Supply DLL Power Supply: +1.8V ±0.1V VSSDL Supply DLL Ground VDDQ Supply DQ Power: +1.8V ±0.1V. VSSQ Supply DQ Ground VREF Supply Reference Voltage for Inputs: +0.
AS4C32M16D2A-25BCN Operation Mode Table 4 shows the truth table for the operation commands. Table 4.
AS4C32M16D2A-25BCN Functional Description Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and continue for a burst length of four or eight in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the active command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A12 select the row).
AS4C32M16D2A-25BCN z Mode Register Set (MRS) The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It controls CAS latency, burst length, burst sequence, test mode, DLL reset, WR, and various vendor specific options to make DDR2 SDRAM useful for various applications.The default value of the mode register is not defined, therefore the mode register must be programmed during initialization for proper operation.
AS4C32M16D2A-25BCN z Extended Mode Register Set (EMRS) - EMR(1) The extended mode register(1) stores the data for enabling or disabling the DLL, output driver strength, ODT value selection and additive latency. The default value of the extended mode register is not defined, therefore the extended mode register must be written after power-up for proper operation.
AS4C32M16D2A-25BCN - EMR(2) The extended mode register (2) controls refresh related features. The default value of the extended mode register (2) is not defined, therefore the extended mode register (2) must be written after power-up for proper operation. The extended mode register(2) is written by asserting LOW on CS#, RAS#, CAS#, WE#, HIGH on BA1 and LOW on BA0, while controlling the states of address pins A0 ~ A12.
AS4C32M16D2A-25BCN - EMR(3) No function is defined in extended mode register(3).The default value of the extended mode register(3) is not defined, therefore the extended mode register(3) must be programmed during initialization for proper operation. Table 8.
AS4C32M16D2A-25BCN z Off-chip drive (OCD) impedance adjustment DDR2 SDRAM supports driver calibration feature and the following flow chart is an example of sequence.Every calibration mode command should be followed by “OCD calibration mode exit” before any other command being issued.All MR should be programmed before entering OCD impedance adjustment and ODT (On Die Termination) should be carefully controlled depending on system environment. Figure 4.
AS4C32M16D2A-25BCN - Extended mode register for OCD impedance adjustment OCD impedance adjustment can be done using the following EMRS mode. In drive mode all outputs are driven out by DDR2 SDRAM. In Drive (1) mode, all DQ, DQS signals are driven HIGH and all DQS# signals are driven LOW. In Drive (0) mode, all DQ, DQS signals are driven LOW and all DQS# signals are drive HIGH. In adjust mode, BL = 4 of operation code data must be used.
AS4C32M16D2A-25BCN z ODT (On Die Termination) On Die Termination (ODT) is a feature that allows a DRAM to turn on/off termination resistance for each DQ, UDQS/UDQS#, LDQS/LDQS#, UDM, and LDM signal via the ODT control pin. The ODT feature is designed to improve signal integrity of the memory channel by allowing the DRAM controller to independently turn on/off termination resistance for any or all DRAM devices. The ODT function is supported for ACTIVE and STANDBY modes.
AS4C32M16D2A-25BCN z Bank activate command The Bank Activate command is issued by holding CAS# and WE# HIGH with CS# and RAS# LOW at the rising edge of the clock. The bank addresses BA0 and BA1 are used to select the desired bank. The row addresses A0 through A12 are used to determine which row to activate in the selected bank. The Bank Activate command must be applied before any Read or Write operation can be executed.
AS4C32M16D2A-25BCN Table 12.
AS4C32M16D2A-25BCN z Write data mask One Write data mask (DM) pin for each 8 data bits (DQ) will be supported on DDR2 SDRAMs, Consistent with the implementation on DDR SDRAMs. It has identical timings on Write operations as the data bits, and though used in a uni-directional manner, is internally loaded identically to data bits to insure matched system timing. DM is not used during read cycles. z Precharge operation The Precharge command is used to precharge or close a bank that has been activated.
AS4C32M16D2A-25BCN z Burst read with auto precharge If A10 is HIGH when a Read Command is issued, the Read with Auto-Precharge function is engaged. The DDR2 SDRAM starts an Auto-Precharge operation on the rising edge which is (AL + BL/2) cycles later from the Read with AP command if tRAS(min) and tRTP are satisfied. If tRAS(min) is not satisfied at the edge, the start point of Auto-Precharge operation will be delayed until tRAS(min) is satisfied.
AS4C32M16D2A-25BCN z Refresh command When CS#, RAS# and CAS# are held LOW and WE# HIGH at the rising edge of the clock, the chip enters the Refresh mode (REF). All banks of the DDR2 SDRAM must be precharged and idle for a minimum of the Precharge time (tRP) before the Refresh command (REF) can be applied. An address counter, internal to the device, supplies the bank address during the refresh cycle. No control of the external address bus is required once this cycle has started.
AS4C32M16D2A-25BCN z Power-Down Power-down is synchronously entered when CKE is registered LOW along with NOP or Deselect command. No read or write operation may be in progress when CKE goes LOW. These operations are any of the following: read burst or write burst and recovery. CKE is allowed to go LOW while any of other operations such as row activation, precharge or autoprecharge, mode register or extended mode register command time, or autorefresh is in progress.
AS4C32M16D2A-25BCN Table 15. Absolute Maximum DC Ratings Symbol Parameter Values Unit Note VDD Voltage on VDD pin relative to Vss -1.0 ~ 2.3 V 1,3 VDDQ Voltage on VDDQ pin relative to Vss -0.5 ~ 2.3 V 1,3 VDDL Voltage on VDDL pin relative to Vss -0.5 ~ 2.3 V 1,3 Voltage on any pin relative to Vss - 0.5 ~ 2.3 V 1,4 VIN, VOUT TSTG Storage temperature - 55~100 1,2 °C NOTE1: Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the devices.
AS4C32M16D2A-25BCN Table 18. Input logic level Symbol Parameter -18 -25/3 Unit Min. Max. Min. Max. VREF + 0.125 VDDQ + 0.3 VREF + 0.125 VDDQ + 0.3 V VIH (DC) DC Input logic High Voltage VIL (DC) DC Input Low Voltage - 0.3 VREF - 0.125 - 0.3 VREF - 0.125 V VIH (AC) AC Input High Voltage VREF + 0.2 - VREF + 0.2 VDDQ + Vpeak V VIL (AC) AC Input Low Voltage - VREF - 0.2 VSSQ - Vpeak VREF - 0.2 V VID (AC) AC Differential Voltage 0.5 VDDQ + 0.6 0.5 VDDQ V 0.5 x VDDQ 0.
AS4C32M16D2A-25BCN Table 22. AC overshoot/undershoot specification for clock, data, strobe, and mask pins (DQ, UDQS, LDQS, UDQS#, LDQS#, DM, CK, CK#) Parameter -18 -25 -3 Unit Maximum peak amplitude allowed for overshoot area 0.5 0.5 0.5 V Maximum peak amplitude allowed for undershoot area 0.5 0.5 0.5 V Maximum overshoot area above VDD 0.19 0.23 0.23 V-ns Maximum undershoot area below VSS 0.19 0.23 0.23 V-ns Table 23.
AS4C32M16D2A-25BCN Table 26. IDD specification parameters and test conditions (VDD = 1.8V ± 0.1V, TOPER = 0~85 °C) Parameter & Test Condition -18 -25 Max.
AS4C32M16D2A-25BCN Table 27. Electrical Characteristics and Recommended A.C. Operating Conditions (VDD = 1.8V ± 0.1V, TOPER= 0~85 °C) Symbol tCK(avg) -18 Parameter Average clock period -25 Min. Max. -3 Min. Max. Min. Max. CL=3 - - 5 8 5 8 CL=4 3.75 8 3.75 8 3.75 8 CL=5 3 8 2.5 8 3 8 CL=6 2.5 8 2.5 8 - CL=7 1.875 8 - - - - tCH(avg) tCL(avg) Average clock HIGH pulse width 0.48 0.52 0.48 0.52 0.48 0.52 Average Clock LOW pulse width 0.48 0.52 0.48 0.
AS4C32M16D2A-25BCN tRTP Internal read to precharge command delay tCKE CKE minimum pulse width tXSNR Exit self refresh to non-read command delay tXSRD Exit self refresh to a read command tXP Exit precharge power down to any command tXARD Exit active power down to read command tXARDS Exit active power down to read command(slow exit, lower power) tAOND ODT turn-on delay tAON ODT turn-on tAONPD ODT turn-on (Power-Down mode) tAOFD ODT turn-off delay tAOF ODT turn-off tAOFPD ODT turn-off
AS4C32M16D2A-25BCN General notes, which may apply for all AC parameters: NOTE 1: DDR2 SDRAM AC timing reference load The below figure represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise representation of the typical system environment or a depiction of the actual load presented by a production tester. Figure 6.
AS4C32M16D2A-25BCN NOTE 4: Differential data strobe DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS “Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timings are measured is mode dependent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF.
AS4C32M16D2A-25BCN NOTE 9:tIS and tIH (input setup and hold) derating For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS(base) and tIH(base) value to the ∆tIS and ∆tIH derating value respectively. Example: tIS (total setup time) = tIS(base) + ∆tIS For slew rates in between the values listed in Tables 29, the derating values may obtained by linear interpolation.These values are typically not subject to production test.
AS4C32M16D2A-25BCN NOTE 18: tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level which specifies when the device output is no longer driving (tHZ), or begins driving (tLZ). NOTE 19: tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (tRPST), or begins driving (tRPRE).
AS4C32M16D2A-25BCN Table 30. Input clock jitter spec parameter Parameter Clock period jitter Symbol Cumulative error across 4 cycles Cumulative error across 5 cycles Cumulative error across n cycles, n=6...10, inclusive Cumulative error across n cycles, n=11...50, inclusive Duty cycle jitter -3 Units Notes Max. Min. Max. Min. Max.
AS4C32M16D2A-25BCN - tJIT(per), tJIT(per,lck) tJIT(per) is defined as the largest deviation of any single tCK from tCK(avg). tJIT(per) = Min/max of {tCKi- tCK(avg) where i=1 to 200} tJIT(per) defines the single period jitter when the DLL is already locked. tJIT(per,lck) uses the same definition for single period jitter, during the DLL locking period only. tJIT(per) and tJIT(per,lck) are not guaranteed through final production testing.
AS4C32M16D2A-25BCN NOTE 37: tQH = tHP – tQHS, where: tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value under the max column. {The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye will be.} NOTE 38: When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(6-10per) of the input clock. (output deratings are relative to the SDRAM input clock.
AS4C32M16D2A-25BCN Timing Waveforms Figure 8. Initialization sequence after power-up tCH tCL CK CK# tIS CKE tIS ODT Command EMR S PRE ALL NOP tRP 400ns PRE ALL MRS tMRD DLL ENABLE tMRD REF tRP REF tRFC tRFC DLL RESET EMR S EMR S MRS tMRD min 200 Cycle Follow OCD Flowchart ANY CMD t OIT OCD CAL.MOD E EXIT OCD Default NOTE 1: To guarantee ODT off, VREF must be valid and a LOW level must be applied to the ODT pin. Figure 9.
AS4C32M16D2A-25BCN Figure 10. OCD adjust mode OCD calibration mode exit OCD adjust mode CMD EMRS NOP NOP NOP NOP EMRS NOP NOP CK# CK WL DQS_in tDS tDH VIH(ac) DQ_in WR DQS# VIH(dc) DT0 DT1 DT2 DT3 VIL(ac) VIL(dc) DM NOTE 1: For proper operation of adjust mode, WL = RL - 1 = AL + CL - 1tCK and tDS /tDH should be met as shown in the figure. NOTE 2: For input data pattern for adjustment, DT0-DT3 is a fixed order and is not affected by burst type (i.e.
AS4C32M16D2A-25BCN Figure 12. ODT update delay timing-tMOD, as measured from outside CK# CK CMD EMRS NOP NOP ODT NOP NOP tIS tAOFD Rtt NOP tAOND tMOD, max New setting Old setting NOTE 1: EMRS command directed to EMR(1), which updates the information in EMR(1)[A6,A2], i.e. Rtt (Nominal). NOTE 2: "setting" in this diagram is measured from outside. Figure 13. ODT timing for active standby mode T0 T1 T3 T2 T4 T5 T6 CK# CK tIS CKE tIS tIS VIH(ac) ODT Internal Term Res.
AS4C32M16D2A-25BCN Figure 14. ODT timing for power-down mode T0 T1 T3 T2 T4 T5 T6 CK# CK CKE tIS tIS VIH(AC) VIL(AC) ODT tAOFPD,max tAOFPD,min Internal Term Res. RTT tAONPD,min tAONPD,max Figure 15. ODT timing mode switch at entering power-down mode T-5 CK# T-4 T-3 T-2 CK T-1 tANPD T0 T1 T2 T3 T4 tIS CKE Entering Slow Exit Active Power Down Mode or Precharge Power Down Mode. ODT tIS VIL(ac) tAOFD Internal Term Res. Active & Standby mode timings to be applied.
AS4C32M16D2A-25BCN Figure 16. ODT timing mode switch at exit power-down mode T0 CK# CK VIH(ac) T1 T4 T5 T6 T7 T8 T9 T10 T11 tAXPD tIS CKE Exiting from Slow Active Power Down Mode or Precharge power Down Mode. tIS ODT Active & Standby mode timings to be applied. VIL(ac) tAOFD Internal Term Res. RTT tIS ODT Power Down mode timings to be applied. VIL(ac) tAOFPD max Internal Term Res. RTT tIS Active & Standby mode timings to be applied. VIH(ac) ODT tAOND RTT Internal Term Res.
AS4C32M16D2A-25BCN Figure 18.1. Posted CAS# operation: AL=2 Read followed by a write to the same bank -1 0 1 2 Active A-Bank Read A-Bank 3 4 5 6 7 8 9 10 11 12 11 12 CK# CK CMD Write A-Bank AL=2 WL=RL-1=4 CL=3 DQS DQS# >=tRCD RL=AL+CL=5 DQ Dout 0 Dout 1 Dout 2 Dout 3 Din 0 Din 1 Din 2 Din 3 [ AL=2 and CL=3, RL= (AL+CL)=5, WL= (RL-1)=4, BL=4] Figure 18.2.
AS4C32M16D2A-25BCN Figure 19. Data output (read) timing tCH CK# CK tCL CK DQS# DQS DQS# DQS tRPRE DQ tRPST tDQSQ max Q Q Q Q tDQSQ max tQH tQH Figure 20.1. Burst read operation: RL=5 (AL=2, CL=3, BL=4) CK# CK CMD T0 T1 Posted CAS# READ A T2 NOP T3 NOP NOP T4 T5 NOP T6 NOP T7 NOP T8 NOP NOP =< tDQSCK DQS DQS# AL=2 CL=3 RL=5 DQs Dout A0 Dout A1 Dout A2 Dout A3 Figure 20.2.
AS4C32M16D2A-25BCN Figure 21.
AS4C32M16D2A-25BCN Figure 23. Read burst interrupt timing: (CL=3, AL=0, RL=3, BL=8) CK# CK CMD Read A NOP NOP Read B NOP NOP NOP NOP NOP NOP DQS DQS# DQs A0 A1 A2 A3 B0 B1 B2 B3 B4 B5 B6 B7 NOTE 1: Read burst interrupt function is only allowed on burst of 8. Burst interrupt of 4 is prohibited. NOTE 2: Read burst of 8 can only be interrupted by another Read command. Read burst interruption by Write command or Precharge command is prohibited.
AS4C32M16D2A-25BCN Figure 25.1. Burst write operation: RL=5 (AL=2, CL=3), WL=4, BL=4 T0 CK# CK T1 Posted CAS# WRITE A CMD T2 NOP T3 NOP T4 NOP Case 1: with tDQSS (max) DQS DQS# T5 T6 NOP NOP tDQSS tDSS tDQSS T7 NOP tDSS Precharge Completion of the Burst Write WL = RL-1 =4 >=tWR DQs DNA0 Case 2: with tDQSS (min) DQS DQS# NOP Tn tDQSS tDSH DNA1 DNA2 DNA3 tDQSS tDSH >=tWR WL = RL-1 =4 DQs DNA0 DNA1 DNA2 DNA3 Figure 25.2.
AS4C32M16D2A-25BCN Figure 26. Burst write followed by burst read: RL=5 (AL=2, CL=3, WL=4, tWTR=2, BL=4) CK# T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 CK Write to Read = CL-1+BL/2+tWTR CKE NOP NOP NOP Post CAS# READ A NOP NOP NOP NOP NOP DQS# DQS DQS# DQS WL = RL-1 = 4 AL=2 CL=3 RL=5 >=tWTR DQ DNA0 DNA1 DNA2 DNA3 DOUT A0 NOTE : The minimum number of clock from the burst write command to the burst read command is [CL-1 + BL/2 + tWTR].
AS4C32M16D2A-25BCN Figure 28. Write burst interrupt timing: (CL=3, AL=0, RL=3, WL=2, BL=8) CK# CK CMD NOP Write A NOP Write B NOP NOP NOP NOP NOP NOP DQS DQS# DQs A0 A1 A2 A3 B0 B1 B2 B3 B4 B5 B6 B7 NOTE 1: Write burst interrupt function is only allowed on burst of 8. Burst interrupt of 4 is prohibited. NOTE 2: Write burst of 8 can only be interrupted by another Write command. Write burst interruption by Read command or Precharge command is prohibited.
AS4C32M16D2A-25BCN Figure 29. Write data mask Data Mask Timing DQS DQS# DQ DM Data Mask Function, WL=3, AL=0, BL=4 shown VIH(ac)VIH(dc) VIH(ac)VIH(dc) VIL(ac)VIL(dc) VIL(ac)VIL(dc) tDS tDH tDS tDH Case 1: min tDQSS CK# CK tWR COMMAND DQS DQS# Write WL tDQSS DQ DM Case 2: max tDQSS tDQSS DQS DQS# DQ DM Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc.
AS4C32M16D2A-25BCN Figure 30.1. Burst read operation followed by precharge: (RL=4, AL=1, CL=3, BL=4, tRTP ≦2 clocks) T0 CK# T1 T2 T3 T4 T5 T6 T7 T8 CK Post CAS# Read A CMD NOP NOP NOP Precharge NOP Bank A Active NOP NOP AL+BL'/2 clks DQS DQS# AL=1 CL=3 >=tRP RL=4 DQ DOUTA0 DOUTA1 DOUTA2 DOUTA3 >=tRAS >=tRTP CL=3 Figure 30.2.
AS4C32M16D2A-25BCN Figure 30.3. Burst read operation followed by precharge: (RL=5, AL=2, CL=3, BL=4, tRTP≦2 clocks) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK# CK CMD Post CAS# READ A NOP NOP NOP NOP Precharge A NOP Bank A Activate NOP AL + BL/2 clks DQS DQS# AL = 2 CL = 3 >=tRP RL= 5 DOUT A0 DQ's >=tRAS DOUT A1 DOUT A2 DOUT A3 CL = 3 >=tRTP Figure 30.4.
AS4C32M16D2A-25BCN Figure 30.5. Burst read operation followed by precharge: (RL=4, AL=0, CL=4, BL=8, tRTP>2 clocks) T0 CK# T1 T2 T3 T4 T5 T6 T7 T8 CK Post CAS# READ A CMD NOP NOP NOP NOP NOP Precharge A NOP Bank A Activate AL + 2 + max( tRTP, 2 tCK)* DQS DQS# CL = 4 AL = 0 >=tRP RL= 4 DQ's DOUT A0 >=tRAS DOUT A1 DOUT A2 DOUT A3 DOUT A4 DOUT A5 DOUT A6 DOUT A7 >=tRTP First 4-bit prefetch Second 4-bit prefetch *: rounded to next integer. Figure 31.1.
AS4C32M16D2A-25BCN Figure 31.2. Burst write followed by precharge: WL= (RL-1) =4 T0 CK# T1 T2 T3 T4 T5 T6 T7 T9 CK Post CAS# Write A CMD NOP NOP NOP NOP NOP NOP NOP Precharge A Completion of the Burst Write >=tWR DQS DQS# WL= 4 DQ's DNA0 DNA1 DNA2 DNA3 Figure 32.1.
AS4C32M16D2A-25BCN Figure 32.2. Burst read operation with auto precharge: (RL=4, AL=1, CL=3, BL=4, tRTP>2 clocks) T0 CK# CK T1 Post CAS# READ A CMD T2 NOP NOP T4 NOP T5 NOP T6 NOP NOP T7 T8 Bank A Activate NOP >= AL+tRTP+tRP Autoprecharge DQS DQS# T3 AL= 1 CL= 3 RL= 4 DQ's DoutA0 DoutA1 DoutA2 DoutA3 tRTP tRP First 4-bit prefetch Precharge begins here Figure 32.3.
AS4C32M16D2A-25BCN Figure 32.4. Burst read operation with auto precharge followed by an activation to the same bank (tRP Limit): (RL=5 (AL=2, CL=3, internal tRCD=3, BL=4, tRTP≦2 clocks) T0 CK# CK T1 T2 T3 T4 T5 T6 T7 T8 A10= 1 Post CAS# READ A CMD NOP NOP NOP >=tRAS(min) NOP NOP Bank A Activate NOP NOP Auto Precharge Begins DQS DQS# AL= 2 >= tRP CL= 3 RL= 5 DQ's DoutA0 DoutA1 DoutA2 DoutA3 CL=3 >= tRC Figure 33.1.
AS4C32M16D2A-25BCN Figure 33.2. Burst write with auto-precharge (WR+tRP): WL=4, WR=2, BL=4, tRP=3 T0 CK# T3 T4 T5 T6 T7 T8 T9 T12 CK A10 = 1 CMD Post CAS# WRA Bank A NOP NOP NOP NOP NOP NOP NOP Bank A Active Completion of the Burst Write Auto Precharge Begins DQS DQS# >=WR >=tRP WL= RL-1=4 DQ's DNA0 DNA1 DNA2 DNA3 >=tRC Figure 34.
AS4C32M16D2A-25BCN Figure 35. Self refresh operation T0 tCH CK# tCK T1 T2 T3 T4 T5 T6 Tm Tn tCL CK >=tXSNR tRP* >=tXSRD CKE VIH(ac) VIL(ac) tAOFD ODT tIS tIS VIL(ac) tIS tIS tIH tIH tIS VIH(ac) Self VIH(dc) VIL(ac) Refresh VIL(dc) CMD tIH NOP NOP NOP Valid NOTE 1 Device must be in the "All banks idle" state prior to entering Self Refresh mode. NOTE 2 ODT must be turned off tAOFD before entering Self Refresh mode, and can be turned on again when tXSRD timing is satisfied.
AS4C32M16D2A-25BCN Figure 37.2.CKE intensive environment CK# CK CKE tCKE tCKE tCKE tXP CMD tCKE tXP REF REF tREFI = 3.9 µs NOTE: The pattern shown above can repeat over a long period of time. With this pattern, DRAM guarantees all AC and DC timing & voltage specifications and DLL operation with temperature and voltage drift Figure 38.
AS4C32M16D2A-25BCN Figure 39. Read with autoprecharge to power-down entry T0 T1 T2 Tx Tx+1 Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Tx+7 Tx+8 Tx+9 Tx+8 Tx+9 CK# CK CMD RDA PRE BL=4 CKE should be kept HIGH until the end of burst operation AL+BL/2 with tRTP = 7.
AS4C32M16D2A-25BCN Figure 41. Write with autoprecharge to power-down entry T0 T1 Tm Tm+1 Tm+2 Tm+3 Tx Tx+1 Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Tx+1 Tx+2 Tx+3 Tx+4 CK# CK CMD WRA PRE BL=4 CKE WL Q DQ Q Q tIS Q WR*1 DQS DQS# T0 T1 Tm Tm+1 Tm+2 Tm+3 Tm+4 Tm+5 Tx CK# CK Start internal Precharge CMD WRA PRE BL=8 CKE WL Q DQ Q Q Q Q Q Q tIS Q WR*1 DQS DQS# *1: WR is programmed through MRS Figure 42.
AS4C32M16D2A-25BCN Figure 44. Precharge/precharge-all command to power-down entry T0 CMD T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 PR or PRA CKE can go to LOW one clock after a Precharge or Precharge all command CKE tIS Figure 45. MRS/EMRS command to power-down entry T0 T1 T2 MRS or EMRS CMD T3 T4 T5 T6 T7 T8 T9 T10 T11 tMRD CKE tIS Figure 46.
AS4C32M16D2A-25BCN Figure 48. 84-Ball 8x12.5x1.2mm(max.) FBGA Package Outline Drawing Information P IN A 1 IN D E X T o p V ie w B o tto m V ie w S id e V ie w D E T A IL : "A " Symbol A A1 A2 A3 D E D1 E1 F e b D2 Dimension in inch Dimension in mm Min Nom Max Min Nom Max --0.047 --1.20 0.010 -0.016 0.25 -0.40 0.030 0.031 0.033 0.75 0.80 0.85 0.005 0.006 0.007 0.125 0.155 0.185 0.311 0.315 0.319 7.9 8.0 8.1 0.488 0.492 0.496 12.4 12.5 12.6 -0.252 --6.40 --0.441 --11.2 --0.126 --3.2 --0.031 --0.80 -0.
AS4C32M16D2A-25BCN ORDERING INFORMATION Alliance Organization VCC Range Package AS4C32M16D2A-25BCN 32M x 16 1.8V 84 Ball FBGA Speed MHz Operating Temp 400 Commercial PART NUMBERING SYSTEM AS4C SDRAM DDR2 32M16D2A 25 32M16=32Mx16 Speed 400MHZ D2A=DDR2 B=BGA Package C Temperature Range 84 ball bga C = Commercial (0 - 95°C) N N = Lead Free RoHS compliant part Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc.
