AS4C32M16MD1A-5BCN Revision History 512Mb AS4C32M16MD1A - 60 ball FBGA PACKAGE Revision Rev 1.0 Rev 1.1 Rev 1.2 Details Preliminary datasheet Removed industrial temperature Adjust the temperature information Date Dec 2015 May 2016 July 2016 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1/56 - Rev.1.
AS4C32M16MD1A-5BCN 1. GENERAL DESCRIPTION This AS4C32M16MD1A-5BCN is 536,870,912 bits synchronous double data rate Dynamic RAM. Each 134,217,728 bits bank is organized as 8,192 rows by 1024 columns by 16 bits fabricated with Alliance Memory’s high performance CMOS technology. This device uses a double data rate architecture to achieve high- speed operation.
AS4C32M16MD1A-5BCN 3. PIN DESCRIPTION FPBGA Assignment Figure 1 — PIN DESCRIPTION Confidential - 3/56 - Rev.1.
AS4C32M16MD1A-5BCN 3.1 Signal Descriptions Table 3 — Signal Descriptions SIGNAL NAME CK,/CK CKE CS RAS/CAS/WE DM, LDM, UDM BA0,BA1 TYPE Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK Input and negative edge of CK. Input and output data is referenced to the crossing of CK and CK (both directions of crossing). Internal clock signals are derived from CK/CK.
AS4C32M16MD1A-5BCN 3.2 Mobile DDR SDRAM Addressing Table Table 4— Addressing Table ITEM 512 Mb 4 BA0,BA1 A10/AP A0-A12 A0-A9 7.8 Number of banks Bank address pins Auto precharge pin X16 Confidential Row addresses Column addresses tREFI(µs) - 5/56 - Rev.1.
AS4C32M16MD1A-5BCN 4. BLOCK DIAGRAM 4.1 Block Diagram Figure.2 — Block Diagram Confidential - 6/56 - Rev.1.
AS4C32M16MD1A-5BCN 4.2 Simplified State Diagram Figure.3 — State Diagram Confidential - 7/56 - Rev.1.
AS4C32M16MD1A-5BCN 5. FUNCTION DESCRIPTION The LPDDR SDRAM is a high speed CMOS, dynamic random-access memory internally configured as a quad-bank DRAM. These devices contain the following number of bits: 512 Mb has 536,870,912 bits The LPDDR SDRAM uses a double data rate architecture to achieve high speed operation. The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins.
AS4C32M16MD1A-5BCN 5.1.1 Initialization Flow Diagram Figure.4 — Flow Diagram Confidential - 9/56 - Rev.1.
AS4C32M16MD1A-5BCN Figure 5 — Initialization Waveform Sequence Confidential - 10/56 - Rev.1.
AS4C32M16MD1A-5BCN 5.2 Register Definition 5.2.1 Mode Register The Mode Register is used to define the specific mode of operation of the LPDDR SDRAM. This definition includes the definition of a burst length, a burst type, a CAS latency as shown below table. The Mode Register is programmed via the MODE REGISTER SET command (with BA0=0 and BA1=0) and will retain the stored information until it is reprogrammed, the device goes into Deep Power-Down mode, or the device loses power.
AS4C32M16MD1A-5BCN 5.2.1.
AS4C32M16MD1A-5BCN Notes: 1. 16-word burst length is optional. 2. For a burst length of two, A1-An selects the two data element block; A0 selects the first access within the block. 3. For a burst length of four, A2-An selects the four data element block; A0-A1 selects the first access within the block. 4. For a burst length of eight, A3-An selects the eight data element block; A0-A2 selects the first access within the block. 5.
AS4C32M16MD1A-5BCN BA1 1 BA0 0 A[n]~A8 Reserved A7 A6 A5 A4 Drive Strength 000b: Full Strength Driver 001b: Half Strength Driver 010b:Quarter Strength Driver 011b:Octant Strength Driver 100b:ThreeQuarters Strength Driver Reserved A3 A2 PASR 000b : 001b : 010b : 101b : A1 A0 All banks 1/2 array(BA1=0) ¼ array(BA1=BA0=0) 1/8 array (BA1 = BA0 = Row Addr MSB = 0) 110b : 1/16 array (BA1=BA0 = Row Addr 2 MSB = 0) 5.2.2.
AS4C32M16MD1A-5BCN 6. COMMANDS All commands (address and control signals) are registered on the positive edge of clock (crossing of CK going high and CK going low). Figure 6 shows basic timing parameters for all commands. Table 7, Table 8 and Table 9 provide a quick reference of available commands. Table 10 and Table 11 provide the current state / next state information. This is followed by a verbal description of each command.
AS4C32M16MD1A-5BCN Table 9 – Truth Table - CKE [Notes 1 - 10] NOTES CKEn-1 CKEn CURRENT STATE COMMANDn ACTIONn L L Power Down X Maintain Power Down L L Self Refresh X Maintain Self Refresh L L Deep Power Down X Maintain Deep Power Down L H Power Down NOP or DESELECT Exit Power Down 5, 6, 9 L H Self Refresh NOP or DESELECT Exit Self Refresh 5, 7, 10 L H Deep Power Down NOP or DESELECT Exit Deep Power Down 5, 8 H L All Banks Idle NOP or DESELECT Precharge Power Down
AS4C32M16MD1A-5BCN Table 10 – Current State BANK n- Command to BANK n CURRENT STATE Any Idle Row Active Read (Auto precharge Disabled) Write (Auto precharge Disabled) CS RAS CAS WE COMMAND ACTION NOTES H X X X DESELECT NOP or Continue previous operation L H H H No Operation NOP or Continue previous operation L L H H ACTIVE Select and activate row L L L H AUTO REFRESH Auto refresh 10 L L L L MRS Mode register set 10 L H L H READ Select column & start read burst
AS4C32M16MD1A-5BCN 10. 11. 12. 13. Precharging All: Starts with the registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, the bank will be in the idle state. Not bank-specific; requires that all banks are idle and no bursts are in progress. Not bank-specific. BURST TERMINATE affects the most recent READ burst, regardless of bank. Requires appropriate DM masking.
AS4C32M16MD1A-5BCN Notes: 1. The table applies when both CKEn-1 and CKEn are HIGH, and after tXSR or tXP has been met if the previous state was Self Refresh or Power Down. 2. DESELECT and NOP are functionally interchangeable. 3. All states and sequences not shown are illegal or reserved. 4. Current State Definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met.
AS4C32M16MD1A-5BCN 7.OPERATION 7.1. Deselect The DESELECT function (/CS HIGH) prevents new commands from being executed by the Mobile DDR SDRAM. The Mobile DDR SDRAM is effectively deselected. Operations already in progress are not affected. 7.2. No Operation The NO OPERATION (NOP) command is used to instruct the selected DDR SDRAM to perform a NOP (/CS = LOW, / RAS = /CAS = /WE = HIGH). This prevents unwanted commands from being registered during idle or wait states.
AS4C32M16MD1A-5BCN 7.3 MODE REGISTER The Mode Register and the Extended Mode Register are loaded via the address inputs. See Mode Register and the Extended Mode Register descriptions for further details. The MODE REGISTER SET command (see Figure 8) can only be issued when all banks are idle and no bursts are in progress, and a subsequent executable command cannot be issued until tMRD (see Figure 9) is met.
AS4C32M16MD1A-5BCN The row remains active until a PRECHARGE command (or READ or WRITE command with Auto Precharge) is issued to the bank. A PRECHARGE command (or READ or WRITE command with Auto Precharge) must be issued before opening a different row in the same bank Figure 10 — Active Command Figure 11 — Bank Activation Command Cycle Confidential - 22/56 - Rev.1.
AS4C32M16MD1A-5BCN 7.5. Read The READ command (see Figure 12) is used to initiate a burst read access to an active row, with a burst length as set in the Mode Register. BA0 and BA1 select the bank, and the address inputs select the starting column location. The value of A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected, the row being accessed will be precharged at the end of the read burst; if Auto Precharge is not selected, the row will remain open for subsequent accesses.
AS4C32M16MD1A-5BCN Figure 13 — Basic Read Timing Parameters Figure 14 — Read Burst Showing CAS Latency 7.5.1 Read to Read Data from a read burst may be concatenated or truncated by a subsequent READ command. The first data from the new burst follows either the last element of a completed burst or the last desired element of a longer burst that is being truncated.
AS4C32M16MD1A-5BCN A READ command can be initiated on any clock cycle following a previous READ command. Non-consecutive Reads are shown in Figure 16. Full-speed random read accesses within a page or pages can be performed as shown in Figure 17. 7.5.2 Read Burst Terminate Data from any READ burst may be truncated with a BURST TERMINATE command, as shown in Figure 18. TheBURST TERMINATE latency is equal to the read (CAS) latency, i.e.
AS4C32M16MD1A-5BCN Figure 16 — Non-Consecutive Read Bursts CK CK Command Address READ NOP NOP READ NOP NOP BA,Col b BA,Col n CL=2 DQS DQ DO n DO b CL=3 DQS DQ DO n = Don't Care 1) DO n (or b) =Data Out from column n (or column b) 2) BA,Col n (or b) =Bank A,Column n (or column b) 3) Burst Length=4; 3 subsequent elements of Data Out appear in the programmed order following DO n (or b) 4) Shown with nominal tAC, tDQSCK and tDQSQ Figure 17 — Random Read Bursts Confidential - 26/56 - Rev.1.
AS4C32M16MD1A-5BCN Figure 18 — Terminating a Read Burst . Figure 19 — Read To Write Confidential - 27/56 - Rev.1.
AS4C32M16MD1A-5BCN Figure 20 — Read To Precharge Confidential - 28/56 - Rev.1.
AS4C32M16MD1A-5BCN 7.5.5 Burst Terminate The BURST TERMINATE command is used to truncate read bursts (with Auto Pre-charge disabled). The most recently registered READ command prior to the BURST TERMINATE command will be truncated. Note that the BURST TERMINATE command is not bank specific. This command should not be used to terminate write bursts. Figure 21 — Burst Terminate Command 7.
AS4C32M16MD1A-5BCN Figure 23 — Basic Write Timing Parameters During Write bursts, the first valid data-in element will be registered on the first rising edge of DQS following the WRITE command, and the subsequent data elements will be registered on successive edges of DQS. The Low state of DQS between the WRITE command and the first rising edge is called the write preamble, and the Low state on DQS following the last data-in element is called the write postamble.
AS4C32M16MD1A-5BCN Figure 24 — Write Burst (min. and max. tDQSS) 7.6.1 Write to Write Data for any WRITE burst may be concatenated with or truncated with a subsequent WRITE command. In either case, a continuous flow of input data, can be maintained. The new WRITE command can be issued on any positive edge of the clock following the previous WRITE command.
AS4C32M16MD1A-5BCN Figure 25 — Concatenated Write Bursts Figure 26 — Non-Consecutive Write Bursts Confidential - 32/56 - Rev.1.
AS4C32M16MD1A-5BCN Figure 27 — Random Write Cycles Figure 28 — Non-Interrupting Write to Read Confidential - 33/56 - Rev.1.
AS4C32M16MD1A-5BCN Figure 29 — Interrupting Write to Read Figure 30 — Non-Interrupting Write to Precharge Confidential - 34/56 - Rev.1.
AS4C32M16MD1A-5BCN Figure 31 — Interrupting Write to Precharge CK CK Command Address WRITE NOP NOP BA,Col b NOP NOP BA a(or BA,Col n all) tWR tDQSSmax *2 DQS DQ PRE DI b DM *1 *1 1) Dl b = Data in to column b. 2) An interrupted burst of 4, 8 or 16 is shown, 2 data elements are written. 3) tWR is referenced from the positive clock edge after the last desired Data In pair.
AS4C32M16MD1A-5BCN 7.8 Auto Precharge Auto Precharge is a feature which performs the same individual bank precharge function as described above, but without requiring an explicit command. This is accomplished by using A10 (A10 = High), to enable Auto Precharge in conjunction with a specific READ or WRITE command. A precharge of the bank / row that is addressed with the READ or WRITE command is automatically performed upon completion of the read or write burst.
AS4C32M16MD1A-5BCN Figure 34 — Self Refresh command Figure 35 — Auto Refresh Cycles Back-to-Back Confidential - 37/56 - Rev.1.
AS4C32M16MD1A-5BCN Figure 36 — Self Refresh Entry and Exit 7.12 Power Down Power-down is entered when CKE is registered Low (no accesses can be in progress). If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CK, CK and CKE.
AS4C32M16MD1A-5BCN Figure 37 — Power-Down Entry and Exit Confidential - 39/56 - Rev.1.
AS4C32M16MD1A-5BCN 7.13 Deep Power Down The Deep Power-Down (DPD) mode enables very low standby currents. All internal voltage generators inside the LPDDR SDRAM are stopped and all memory data is lost in this mode. All the information in the Mode Register and the Extended Mode Register is lost. Deep Power-Down is entered using the BURST TERMINATE command (see Figure 21) except that CKE is registered Low. All banks must be in idle state with no activity on the data bus prior to entering the DPD mode.
AS4C32M16MD1A-5BCN 7.14 Clock Stop Stopping a clock during idle periods is an effective method of reducing power consumption.
AS4C32M16MD1A-5BCN 8. ELECTRICAL CHARACTERISTIC 8.1 Absolute Maximum Ratings VALUES PARAMETER SYMBOL UNITS MIN MAX VDD −0.3 2.7 V Voltage on VDDQ relative to VSS VDDQ −0.3 2.7 V Voltage on any pin relative to VSS VIN, VOUT −0.3 2.7 V Tj -30 +85 °C Storage Temperature TSTG −55 +150 °C Short Circuit Output Current IOUT ±50 mA PD 1.0 W Voltage on VDD relative to VSS Operating temperature : Power Dissipation 8.
AS4C32M16MD1A-5BCN 8.3 Electrical Characteristics and AC/DC Operating Conditions All values are recommended operating conditions unless otherwise noted. 8.3.1 Electrical Characteristics and AC/DC Operating Conditions (VDD/VDDQ: 1.7~1.95V) PARAMETER/CONDITION Supply Voltage I/O Supply Voltage SYMBOL MIN MAX UNITS VDD VDDQ 1.70 1.70 1.95 1.95 V V NOTES ADDRESS AND COMMAND INPUTS (A0~An, BA0,BA1,CKE, CS, RAS , CAS , WE ) Input High Voltage VIH 0.8*VDDQ VDDQ + 0.3 V Input Low Voltage VIL −0.3 0.
AS4C32M16MD1A-5BCN 8.4 IDD Specification Parameters and Test Conditions 8.4.
AS4C32M16MD1A-5BCN Notes: 1. IDD specifications are tested after the device is properly initialized. 2. Input slew rate is 1V/ns. 3. Definitions for IDD: LOW is defined as VIN ≤ 0.1 * VDDQ; HIGH is defined as VIN ≥ 0.9 * VDDQ; STABLE is defined as inputs stable at a HIGH or LOW level; SWITCHING is defined as: - Address and command: inputs changing between HIGH and LOW once per two clock cycles; - Data bus inputs: DQ changing between HIGH and LOW once per clock cycle; DM and DQS are STABLE. 4.
AS4C32M16MD1A-5BCN 8.5 AC Timings 8.5.
AS4C32M16MD1A-5BCN PARAMETER SYMBOL -5 NOTES ns tCK ns ns 24 25 tRCD tRP tRRD tWR Auto precharge write recovery + precharge time tDAL - tCK Internal write to Read command delay tWTR 1 tCK Self Refresh exit to next valid command delay tXSR 120 ns 26 tXP 2 tCK 27 tCKE 1 tCK ACTIVE to READ or WRITE delay PRECHARGE command period ACTIVE bank A to ACTIVE bank B delay WRITE recovery time Exit power down to next valid command delay CKE min.
AS4C32M16MD1A-5BCN one transition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers. 12. The only time that the clock frequency is allowed to change is during clock stop, power-down or self-refresh modes. 13.
AS4C32M16MD1A-5BCN Confidential - 49/56 - Rev.1.
AS4C32M16MD1A-5BCN 8.5.2 Output Slew Rate Characteristics PARAMETER Pull-up and Pull-Down Slew Rate for Full Strength Driver Pull-up and Pull-Down Slew Rate for Three-Quarter Strength Driver Pull-up and Pull-Down Slew Rate for Half Strength Driver Output Slew rate Matching ratio (Pull-up to Pull-down) MIN 0.7 0.5 0.3 0.7 MAX 2.5 1.75 1.0 1.4 UNIT V/ns V/ns V/ns - NOTES 1,2 1,2 1,2 3 Notes: 1. Measured with a test load of 20 pF connected to VSSQ. 2.
AS4C32M16MD1A-5BCN 8.5.4 AC Overshoot and Undershoot Definition Figure 40 — AC Overshoot and Undershoot Definition Confidential - 51/56 - Rev.1.
AS4C32M16MD1A-5BCN 9. PACKAGE DIMENSION 60Ball Fine Pitch BGA (8.0x9.0mm) Confidential - 52/56 - Rev.1.
AS4C32M16MD1A-5BCN PART NUMBERING SYSTEM AS4C 32M16MD1A 5 32M16=32Mx16 MD1=Mobile DDR1 5= 200MHz DRAM A=A Die B B = FPBGA (Fine Pitch Ball Grid Array) C C=Extended (-30°C +85°C) N Indicates Pb and Halogen Free Alliance Memory, Inc. 511 Taylor Way, San Carlos, CA 94070 Tel: 650-610-6800 Fax: 650-620-9211 www.alliancememory.com Copyright © Alliance Memory All Rights Reserved © Copyright 2007 Alliance Memory, Inc. All rights reserved.
