Datasheet

ManualsBrandsAlliance Memory ManualsDRAMDRAM 512MB 5.4ns TSOP-II

Revision History

AS4C32M16SB-7TCN/AS4C32M16SB-7TIN/AS4C32M16SB-6TIN- 54pin TSOPII PACKAGE

Revision Details Date

Rev 1.0 Preliminary datasheet Jun 2016

Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211

Alliance Memory Inc. reserves the right to change products or specification without notice

AS4C32M16SB-6TIN

AS4C32M16SB-7TIN

AS4C32M16SB-7TCN

Confidential

- 1/55 -

Rev.1.0 June 2016

Summary of content (55 pages)

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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN Revision History AS4C32M16SB-7TCN/AS4C32M16SB-7TIN/AS4C32M16SB-6TIN- 54pin TSOPII PACKAGE Revision Rev 1.0 Details Preliminary datasheet Date Jun 2016 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential - 1/55 - Rev.1.
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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN Overview Features • • • • • • • • • • • • • Fast access time from clock: 5/5.4 ns Fast clock rate: 166/143 MHz Fully synchronous operation Internal pipelined architecture 8M word x 16-bit x 4-bank Programmable Mode registers - CAS Latency: 2 or 3 - Burst Length: 1, 2, 4, 8, or full page - Burst Type: Sequential or Interleaved - Burst stop function Auto Refresh and Self Refresh 8192 refresh cycles/64ms CKE power down mode Single +3.3V ±0.
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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN Figure 1. Pin Assignment (Top View) VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD LDQM WE# CAS# RAS# CS# BA0 BA1 A10/AP A0 A1 A2 A3 VDD Confidential 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 - 3/55 - VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS NC UDQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 VSS Rev.1.
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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN Figure 2.
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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN Pin Descriptions Table 3. Pin Details Symbol Type Description CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. CKE Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.
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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN DQ0-DQ15 Input / Output NC - VDDQ Suply DQ Power: Provide isolated power to DQs for improved noise immunity. (+3.3V ±0.3V) VSSQ Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity. (0 V) VDD Supply Power Supply: +3.3V ±0.3V VSS Supply Ground Confidential Data I/O: The DQ0-15 input and output data are synchronized with the positive edges of CLK. The I/Os are maskabled during Reads and Writes.
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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN Operation Mode Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 4 shows the truth table for the operation commands. Table 4.
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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN Commands 1 BankActivate (RAS# = "L", CAS# = "H", WE# = "H", BAs = Bank, A0-A12 = Row Address) The BankActivate command activates the idle bank designated by the BA0, 1 signals. By latching the row address on A0 to A12 at the time of this command, the selected row access is initiated. The read or write operation in the same bank can occur after a time delay of tRCD(min.) from the time of bank activation.
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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN T1 T0 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND READ A NOP NOP CAS# Latency=2 tCK2, DQ DOUT A0 CAS# Latency=3 tCK3, DQ NOP NOP NOP NOP DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 NOP NOP DOUT A3 Figure 4. Burst Read Operation (Burst Length = 4, CAS# Latency = 2, 3) The read data appears on the DQs subject to the values on the DQM inputs two clocks earlier (i.e. DQM latency is two clocks for output buffers).
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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK DQM COMMAND NOP NOP READ A NOP NOP CAS# Latency=2 tCK2, DQ WRITE B NOP NOP NOP DIN B0 DIN B1 DIN B2 DIN B3 Must be Hi-Z before the Write Command Don’t Care Figure 7.
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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN 5 Read and AutoPrecharge command (RAS# = "H", CAS# = "L", WE# = "H", BAs = Bank, A10 = "H", A0-A9 = Column Address) The Read and AutoPrecharge command automatically performs the precharge operation after the read operation. Once this command is given, any subsequent command cannot occur within a time delay of {tRP(min.) + burst length}. At full-page burst, only the read operation is performed in this command and the auto precharge function is ignored.
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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND NOP WRITE A READ B CAS# Latency=2 tCK2, DQ DIN A0 don’t care CAS# Latency=3 tCK3, DQ DIN A0 don’t care NOP NOP NOP DOUT B0 DOUT B1 DOUT B2 DOUT B3 DOUT B0 DOUT B1 DOUT B2 don’t care NOP NOP NOP DOUT B3 Input data must be removed from the DQ at least one clock cycle before the Read data appears on the outputs to avoid data contention Figure 12.
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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 CLK Bank A Activate COMMAND NOP NOP WRITE A Auto Precharge NOP NOP NOP NOP NOP Bank A Activate tDAL DQ DIN A0 DIN A1 tDAL=tWR+tRP Begin AutoPrecharge Bank can be reactivated at completion of tDAL Figure 14.
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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CLK CKE tMRD CS# RAS# CAS# WE# BA0,1 A10 Address Key A0-A9, A11-A12 DQM DQ tRP Hi-Z PrechargeAll Mode Register Set Command Any Command Don’t Care Figure 15. Mode Register Set Cycle • Burst Length Field (A2~A0) This field specifies the data length of column access using the A2~A0 pins and selects the Burst Length to be 2, 4, 8, or full page. Table 6.
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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN • Burst Type Field (A3) The Addressing Mode can be one of two modes, Interleave Mode or Sequential Mode. Sequential Mode supports burst length of 1, 2, 4, 8, or full page, but Interleave Mode only supports burst length of 4 and 8. Table 7. Addressing Mode Select Field A3 Burst Type 0 Sequential 1 Interleave • Burst Definition, Addressing Sequence of Sequential and Interleave Mode Table 8.
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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN • Test Mode field (A8~A7) These two bits are used to enter the test mode and must be programmed to "00" in normal operation. Table 10. Test Mode A8 A7 Test Mode 0 0 normal mode 0 1 Vendor Use Only 1 X Vendor Use Only • Write Burst Length (A9) This bit is used to select the write burst length. When the A9 bit is "0", the Burst-Read-Burst-Write mode is selected. When the A9 bit is "1", the Burst-Read-Single-Write mode is selected. Table 11.
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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND DQ NOP WRITE A NOP NOP Burst Stop DIN A0 DIN A1 DIN A2 don’t care NOP NOP NOP NOP Figure 17. Termination of a Burst Write Operation (Burst Length = X) 11 Device Deselect command (CS# = "H") The Device Deselect command disables the command decoder so that the RAS#, CAS#, WE# and Address inputs are ignored, regardless of whether the CLK is enabled.
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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN 16 Clock Suspend Mode Exit / PowerDown Mode Exit command (CKE= "H") When the internal CLK has been suspended, the operation of the internal CLK is reinitiated from the subsequent cycle by providing this command (asserting CKE "HIGH", the command should be NOP or deselect). When the device is in the PowerDown mode, the device exits this mode and all disabled buffers are turned on to the active state. tPDE (min.
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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN Table 12. Absolute Maximum Rating Symbol Item VIN, VOUT Input, Output Voltage VDD, VDDQ Power Supply Voltage TA Ambient Temperature TSTG Storage Temperature TSOLDER Values Unit Note -1.0 ~ 4.6 V 1 -1.0 ~ 4.6 V 1 Commercial 0 ~ 70 °C 1 Industrial -40 ~ 85 °C 1 -55 ~ 150 °C 1 260 °C 1 Soldering Temperature (10 seconds) PD Power Dissipation 1 W 1 IOS Short Circuit Output Current 50 mA 1 Table 13. Recommended D.C.
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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN Table 15. D.C. Characteristics (VDD = 3.3V ± 0.3V, TA = -40~85°C) Symbol Description/Test condition -6 -7 Max.
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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN Table 16. Electrical Characteristics and Recommended A.C. Operating Conditions (VDD = 3.3V ± 0.3V, TA = -40~85°C) (Note: 5, 6, 7, 8) Symbol -6 A.C. Parameter -7 Min. Max. Min. Max.
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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN Table 17. LVTTL Interface Reference Level of Output Signals 1.4V / 1.4V Output Load Reference to the Under Output Load (B) Input Signal Levels 2.4V / 0.4V Transition Time (Rise and Fall) of Input Signals 1ns Reference Level of Input Signals 1.4V 1.4V 3.3V 50Ω 1.2KΩ Output Output 30pF Z0=50Ω 870Ω Figure 18.1 LVTTL D.C. Test Load (A) 30pF Figure 18.2 LVTTL A.C. Test Load (B) 7. Transition times are measured between VIH and VIL.
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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN Timing Waveforms Figure 19.
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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN Figure 20.
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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN Figure 21. Auto Refresh (Burst Length=4, CAS# Latency=2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9, A11-A12 RAx tRP tRC tRC CAx tRCD DQM DQ Ax0 Precharge All Command Auto Refresh Command Auto Refresh Command Activate Command Bank A Ax1 Read Command Bank A Don’t Care Confidential - 25/55 - Rev.1.
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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN Figure 22.
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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN Figure 23. Self Refresh Entry & Exit Cycle T0 T1 T2 T3 T4 CLK *Note 1 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 *Note 2 CKE tXSR *Note 5 *Note 3,4 *Note 8 tPDE tIS tIH *Note 6 tIS CS# *Note 7 RAS# *Note 9 CAS# WE# BA0,1 A10 A0-A9, A11-A12 DQM DQ Hi-Z Hi-Z Self Refresh Exit Self Refresh Entry Auto Refresh Don’t Care Note: To Enter SelfRefresh Mode 1. CS#, RAS# & CAS# with CKE should be low at the same clock cycle. 2.
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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN Figure 24.1. Clock Suspension During Burst Read (Using CKE) (Burst Length=4, CAS# Latency=2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9, A11-A12 RAx CAx DQM DQ tHZ Hi-Z Ax0 Activate Command Bank A Read Command Bank A Ax1 Clock Suspend 1 Cycle Ax2 Clock Suspend 2 Cycles Ax3 Clock Suspend 3 Cycles Don’t Care Confidential - 28/55 - Rev.1.
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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN Figure 24.2. Clock Suspension During Burst Read (Using CKE) (Burst Length=4, CAS# Latency=3) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9, A11-A12 RAx CAx DQM DQ tHZ Hi-Z Ax0 Activate Command Bank A Read Command Bank A Ax1 Ax2 Clock Suspend 1 Cycle Clock Suspend 2 Cycles Ax3 Clock Suspend 3 Cycles Don’t Care Confidential - 29/55 - Rev.1.
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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN Figure 25. Clock Suspension During Burst Write (Using CKE) (Burst Length=4) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9, A11-A12 RAx CAx DQM DQ Hi-Z DAx0 Activate Command Bank A Confidential DAx1 Clock Suspend 1 Cycle Write Command Bank A DAx2 Clock Suspend 2 Cycles DAx3 Clock Suspend 3 Cycles Don’t Care - 30/55 - Rev.1.
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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN Figure 26.
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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN Figure 27.1.
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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN Figure 27.2.
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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN Figure 28.
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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN Figure 29.1.
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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN Figure 29.2.
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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN Figure 30.
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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN Figure 31.1.
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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN Figure 31.2.
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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN Figure 32.1.
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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN Figure 32.2.
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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN Figure 33.
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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN Figure 34.1.
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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN Figure 34.2.
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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN Figure 35.
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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN Figure 36.1.
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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN Figure 36.2.
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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN Figure 37.
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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN Figure 38.
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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN Figure 39.
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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN Figure 40.
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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN Figure 41.
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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN Figure 42.
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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN Figure 43. 54 Pin TSOP II Package Outline Drawing Information Symbol A A1 A2 B C D E e HE L L1 S y θ Confidential Dimension in inch Min Nom Max Dimension in mm Min Nom Max --0.002 0.035 0.01 0.004 0.87 0.395 --0.455 0.016 --0.05 0.9 0.25 0.12 22.09 10.03 --11.56 0.4 ------0° ----0° ----0.039 0.014 0.006 0.875 0.400 0.031 0.463 0.02 0.032 0.028 ----- 0.047 0.008 0.043 0.018 0.008 0.88 0.405 --0.471 0.024 ----0.004 8° - 54/55 - ----1.0 0.35 0.
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AS4C32M16SB-6TIN AS4C32M16SB-7TIN AS4C32M16SB-7TCN PART NUMBERING SYSTEM AS4C 32M16SB 6/7 DRAM 32M16=32Mx16 S = SDRAM B=B die 6=166MHz 7=143MHz T C/I N T = TSOPII C=Commercial (0° C~+70° C) I = Industrial (-40° C~+85° C) Indicates Pb and Halogen Free Alliance Memory, Inc. 511 Taylor Way, San Carlos, CA 94070 Tel: 650-610-6800 Fax: 650-620-9211 www.alliancememory.com Copyright © Alliance Memory All Rights Reserved © Copyright 2007 Alliance Memory, Inc. All rights reserved.