Datasheet

CLK
COMMAND
T0
T1 T2 T3 T4 T5 T6
NOP WRITE A READ B NOP NOP NOP NOP NOP
T7 T8
NOP
CAS# Latency=2
t
CK2
, DQ
CAS# Latency=3
t
CK3
, DQ
DOUT B
0
DOUT B
1
DOUT B
2
DOUT B
3
DOUT B
0
DOUT B
1
DOUT B
2
DOUT B
3
DIN A
0
don’t care
DIN A
0
don’t care don’t care
Input data must be removed from the DQ at
least one clock cycle before the Read data
appears on the outputs to avoid data contention
Figure 12. Write Interrupted by a Read
(Burst Length = 4, CAS# Latency = 2, 3)
The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto
precharge function should be issued m cycles after the clock edge in which the last data-in element is
registered, where m equals t
WR
/t
CK
rounded up to the next whole number. In addition, the DQM signals
must be used to mask input data, starting with the clock edge following the last data-in element and
ending with the clock edge on which the BankPrecharge/PrechargeAll command is entered (refer to the
following figure).
CLK
COMMAND
T0
T1 T2 T3 T4 T5 T6
WRITE NOP NOP
Precharge
NOP NOP Activate NOP
T7
DQM
Don’t Care
ADDRESS
Bank
Col n
Bank (s)
ROW
t
RP
DIN
n
DIN
N+1
t
WR
DQ
Note: The DQMs can remain low in this example if the length of the write burst is 1 or 2.
Figure 13. Write to Precharge
7 Write and AutoPrecharge command
(RAS# = "H", CAS# = "L", WE# = "L", BAs = Bank, A10 = "H", A0-A9 = Column Address)
The Write and AutoPrecharge command performs the precharge operation automatically after the
write operation. Once this command is given, any subsequent command can not occur within a time
delay of {(burst length -1) + t
WR
+ t
RP
(min.)}. At full-page burst, only the write operation is performed in
this command and the auto precharge function is ignored.
AS4C32M16SB-6TIN
AS4C32M16SB-7TIN
AS4C32M16SB-7TCN
Confidential
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Rev.1.0 June 2016