Datasheet

ManualsBrandsAlliance Memory ManualsDRAMDRAM 8GB 1.25ns TFBGA

Table Of Contents

Revision History 8Gb: x4, x8, x16 DDR3L SDRAM

AS4C2GM4D3L– 256 Meg x 4 x 8 banks*

AS4C1G8MD3L– 128 Meg x 8 x 8 banks

AS4C512M16D3L – 64 Meg x 16 x 8 banks

Revision

Details

Date

Rev 1.0

Preliminary datasheet

February 2016

Rev 2.0

Amend Table 1 noted.

June 2016

Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070

TEL: (650) 610-6800 FAX: (650) 620-9211

Alliance Memory Inc. reserves the right to change products or specification without notice.

8Gb: x4, x8, x16 DDR3L SDRAM

Description

* not released yet

Summary of content (209 pages)

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8Gb: x4, x8, x16 DDR3L SDRAM Description Revision History 8Gb: x4, x8, x16 DDR3L SDRAM AS4C2GM4D3L– 256 Meg x 4 x 8 banks* AS4C1G8MD3L– 128 Meg x 8 x 8 banks AS4C512M16D3L – 64 Meg x 16 x 8 banks Revision Rev 1.0 Rev 2.0 Details Preliminary datasheet Amend Table 1 noted. Date February 2016 June 2016 * not released yet Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc.
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8Gb: x4, x8, x16 DDR3L SDRAM Description DDR3L SDRAM AS4C2GM4D3L– 256 Meg x 4 x 8 banks* AS4C1G8MD3L– 128 Meg x 8 x 8 banks AS4C512M16D3L – 64 Meg x 16 x 8 banks • TC of 0°C to +95°C – 64ms, 8192-cycle refresh at 0°C to +85°C – 32ms at +85°C to +95°C • Self refresh temperature (SRT) • Automatic self refresh (ASR) • Write leveling • Multipurpose register • Output driver calibration Features • VDD = V DDQ = 1.35V (1.283–1.45V) • Backward compatible to V DD = V DDQ = 1.5V ±0.
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8Gb: x4, x8, x16 DDR3L SDRAM Description Table 2: Addressing Parameter Configuration 2 Gig x 4 1 Gig x 8 512 Meg x 16 256 Meg x 4 x 8 banks 128 Meg x 8 x 8 banks 64 Meg x 16 x 8 banks Refresh count 8K 8K 8K Row address 64K (A[15:0]) 64K (A[15:0]) 64K (A[15:0]) Bank address 8 (BA[2:0]) 8 (BA[2:0]) 8 (BA[2:0]) 4K (A[13,11, 9:0]) 2K (A[11,9:0]) 1K (A[9:0]) 2KB 2KB 2KB Column address Page size Figure 1: DDR3L Part Numbers AS4C512M16D3L-12BCN Example Part Number: Configuration Speed
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8Gb: x4, x8, x16 DDR3L SDRAM Description Contents State Diagram ................................................................................................................................................ 11 Functional Description ................................................................................................................................... 12 Industrial Temperature ......................................................................................................................
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8Gb: x4, x8, x16 DDR3L SDRAM Description Input Clock Frequency Change ...................................................................................................................... 119 Write Leveling ............................................................................................................................................... 121 Write Leveling Procedure ...........................................................................................................................
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8Gb: x4, x8, x16 DDR3L SDRAM Description ODT Latency and Posted ODT .................................................................................................................... 195 Timing Parameters .................................................................................................................................... 195 ODT Off During READs ..............................................................................................................................
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8Gb: x4, x8, x16 DDR3L SDRAM Description List of Figures Figure 1: DDR3L Part Numbers ........................................................................................................................ 2 Figure 2: Simplified State Diagram ................................................................................................................. 11 Figure 3: 2 Gig x 4 Functional Block Diagram ..................................................................................................
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Gb: x4, x8, x16 DDR3L SDRAM Description Figure 51: READ Latency .............................................................................................................................. 134 Figure 52: Mode Register 1 (MR1) Definition ................................................................................................. 135 Figure 53: READ Latency (AL = 5, CL = 6) .......................................................................................................
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8Gb: x4, x8, x16 DDR3L SDRAM Description Figure 103: Figure 104: Figure 105: Figure 106: Figure 107: Figure 108: Figure 109: Figure 110: Figure 111: Figure 112: Figure 113: Figure 114: Figure 115: Figure 116: Figure 117: Figure 118: Figure 119: MRS Command to Power-Down Entry ......................................................................................... 183 Power-Down Exit to Refresh to Power-Down Entry ....................................................................... 184 RESET Sequence ..
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8Gb: x4, x8, x16 DDR3L SDRAM Description List of Tables Table 1: Key Timing Parameters ....................................................................................................................... 1 Table 2: Addressing ......................................................................................................................................... 2 Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions .............................................................................................
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8Gb: x4, x8, x16 DDR3L SDRAM Description Table 51: Table 52: Table 53: Table 54: Table 55: Table 56: Table 57: Table 58: Table 59: Table 60: Table 61: Table 62: Table 63: Table 64: Table 65: Table 66: Table 67: Table 68: Table 69: Table 70: Table 71: Table 72: Table 73: Table 74: Table 75: Table 76: Table 77: Table 78: Table 79: Table 80: Table 81: Table 82: Table 83: Table 84: Table 85: Table 86: Table 87: Table 88: Table 89: DDR3L-1333 Speed Bins ..........................................................
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8Gb: x4, x8, x16 DDR3L SDRAM State Diagram State Diagram Figure 2: Simplified State Diagram CKE L Power applied Power on MRS, MPR, write leveling Initialization Reset procedure Self refresh SRE ZQCL From any state RESET ZQ calibration MRS SRX REF ZQCL/ZQCS Refreshing Idle PDE ACT PDX Active powerdown Precharge powerdown Activating PDX CKE L CKE L PDE Bank active WRITE WRITE READ WRITE AP READ AP READ Writing READ WRITE WRITE AP Reading READ AP WRITE AP READ AP PRE, PREA
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8Gb: x4, x8, x16 DDR3L SDRAM Functional Description Functional Description DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins.
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8Gb: x4, x8, x16 DDR3L SDRAM Functional Description • Complete functionality may be described throughout the document; any page or diagram may have been simplified to convey a topic and may not be inclusive of all requirements. • Any specific requirement takes precedence over a general statement. • Any functionality not specifically stated is considered undefined, illegal, and not supported, and can result in unknown operation. • Row addressing is denoted as A[n:0].
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8Gb: x4, x8, x16 DDR3L SDRAM Functional Block Diagrams Functional Block Diagrams DDR3 SDRAM is a high-speed, CMOS dynamic random access memory. It is internally configured as an 8-bank DRAM.
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8Gb: x4, x8, x16 DDR3L SDRAM Functional Block Diagrams Figure 4: 1 Gig x 8 Functional Block Diagram ODT control ODT ZQ RZQ Control logic CKE VSSQ To ODT/output drivers ZQ CAL RESET# ZQCL, ZQCS A12 VDDQ/2 CK, CK# BC4 (burst chop) Command decode CS# RAS# CAS# WE# OTF Mode registers Refresh counter CK, CK# sw1 (1 . . .
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8Gb: x4, x8, x16 DDR3L SDRAM Ball Assignments and Descriptions Ball Assignments and Descriptions Figure 6: 78-Ball FBGA – x4, x8 (Top View) 1 2 3 VSS VDD VSS VDDQ 4 5 6 7 8 9 NC NF, NF/TDQS# VSS VDD VSSQ DQ0 DM, DM/TDQS VSSQ VDDQ DQ2 DQS DQ1 DQ3 VSSQ NF, DQ6 DQS# VDD VSS VSSQ A B C D VSSQ E VREFDQ NF, DQ7 NF, DQ5 VDDQ NF, DQ4 VDDQ F NC VSS RAS# CK VSS NC ODT VDD CAS# CK# VDD CKE NC CS# WE# A10/AP ZQ NC VSS BA0 BA2 A15 VREFCA VSS VDD A3 A0 A12/
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8Gb: x4, x8, x16 DDR3L SDRAM Ball Assignments and Descriptions Figure 7: 96-Ball FBGA – x16 (Top View) 1 2 3 VDDQ DQ13 VSSQ 4 5 6 7 8 9 DQ15 DQ12 VDDQ VSS VDD VSS UDQS# DQ14 VSSQ VDDQ DQ11 DQ9 UDQS DQ10 VDDQ VSSQ VDDQ UDM DQ8 VSSQ VDD VSS VSSQ DQ0 LDM VSSQ VDDQ VDDQ DQ2 LDQS DQ1 DQ3 VSSQ VSSQ DQ6 LDQS# VDD VSS VSSQ VREFDQ VDDQ DQ4 DQ7 DQ5 VDDQ NC VSS RAS# CK VSS NC ODT VDD CAS# CK# VDD CKE NC CS# WE# A10/AP ZQ NC VSS BA0 BA2 A15
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8Gb: x4, x8, x16 DDR3L SDRAM Ball Assignments and Descriptions Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions Symbol Type Description A[15:13], A12/BC#, A11, A10/AP, A[9:0] Input Address inputs: Provide the row address for ACTIVATE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank.
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8Gb: x4, x8, x16 DDR3L SDRAM Ball Assignments and Descriptions Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions (Continued) Symbol Type DQ[3:0] I/O Data input/output: Bidirectional data bus for the x4 configuration. DQ[3:0] are referenced to VREFDQ. Description DQ[7:0] I/O Data input/output: Bidirectional data bus for the x8 configuration. DQ[7:0] are referenced to VREFDQ. DQS, DQS# I/O Data strobe: Output with read data. Edge-aligned with read data. Input with write data.
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8Gb: x4, x8, x16 DDR3L SDRAM Ball Assignments and Descriptions Table 4: 96-Ball FBGA – x16 Ball Descriptions Symbol Type Description A[15:13], A12/BC#, A11, A10/AP, A[9:0] Input Address inputs: Provide the row address for ACTIVATE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank.
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8Gb: x4, x8, x16 DDR3L SDRAM Ball Assignments and Descriptions Table 4: 96-Ball FBGA – x16 Ball Descriptions (Continued) Symbol Type Description RESET# Input Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input receiver is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × VDD and DC LOW ≤ 0.2 × VDDQ. RESET# assertion and desertion are asynchronous. UDM Input Input data mask: UDM is an upper-byte, input mask signal for write data.
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8Gb: x4, x8, x16 DDR3L SDRAM Package Dimensions Package Dimensions Figure 8: 78-Ball FBGA – x4, x8 (SN) 0.155 Seating plane A 0.12 A 1.8 CTR Nonconductive overmold 78X Ø0.47 Dimensions apply to solder balls post-reflow on Ø0.42 SMD ball pads. Ball A1 ID (covered by SR) 9 8 7 Ball A1 ID 3 2 1 A B C D E F G H J K L M N 13.2 ±0.1 9.6 CTR 0.8 TYP 1.1 ±0.1 0.8 TYP 6.4 CTR 0.28 MIN 9 ±0.1 Notes: 1. All dimensions are in millimeters. 2. Solder ball material: SAC302 (96.8% Sn, 3% Ag, 0.2% Cu). Rev.2.
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8Gb: x4, x8, x16 DDR3L SDRAM Package Dimensions Figure 9: 96-Ball FBGA – x16 (HA) 0.155 Seating plane A 0.12 A 1.8 CTR Nonconductive overmold 96X Ø0.47 Dimensions apply to solder balls postreflow on Ø0.42 SMD ball pads. Ball A1 ID (covered by SR) 9 8 7 Ball A1 ID 3 2 1 A B C D E F G H J K L M N P R T 14 ±0.1 12 CTR 0.8 TYP 1.1 ±0.1 0.8 TYP 6.4 CTR 0.29 MIN 9 ±0.1 Notes: 1. All dimensions are in millimeters. 2. Solder ball material: SAC302 (96.8% Sn, 3% Ag, 0.2% Cu). Rev.2.
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8Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications Electrical Specifications Absolute Ratings Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability.
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8Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications Input/Output Capacitance Table 6: DDR3L Input/Output Capacitance Note 1 applies to the entire table DDR3L -800 Capacitance DDR3L -1066 DDR3L -1333 DDR3L -1600 DDR3L -1866 DDR3L -2133 Parameters Sym Min Max Min Max Min Max Min Max Min Max Min CK and CK# CCK 0.8 1.6 0.8 1.6 0.8 1.4 0.8 1.4 0.8 1.3 0.8 1.3 pF ΔC: CK to CK# CDCK 0.0 0.15 0.0 0.15 0.0 0.15 0.0 0.15 0.0 0.15 0.0 0.15 pF CIO 1.4 2.5 1.4 2.
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8Gb: x4, x8, x16 DDR3L SDRAM Thermal Characteristics Thermal Characteristics Table 7: Thermal Characteristics Parameter/Condition Value Units Symbol Notes Operating case temperature Commercial 0 to +85 °C TC 1, 2, 3 0 to +95 °C TC 1, 2, 3, 4 Operating case temperature Industrial –40 to +85 °C TC 1, 2, 3 –40 to +95 °C TC 1, 2, 3, 4 °C/W ΘJC 5 Junction-to-case (TOP) Die Rev A 78-ball “SN” 3.2 96-ball “HA” 3.0 1. MAX operating case temperature.
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8Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications – I DD Specifications and Conditions Electrical Specifications – I DD Specifications and Conditions Within the following IDD measurement tables, the following definitions and conditions are used, unless stated otherwise: LOW: V IN ≤ V IL(AC)max; HIGH: V IN ≥ V IH(AC)min. Midlevel: Inputs are V REF = V DD/2. RON set to RZQ/7 (34Ω RTT,nom set to RZQ/6 (40Ω RTT(WR) set to RZQ/2 (120Ω QOFF is enabled in MR1.
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8Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications – I DD Specifications and Conditions 0 0 – 0 0 0 – 2 D 1 0 0 0 0 0 0 0 0 0 0 – 3 D# 1 1 1 1 0 0 0 0 0 0 0 – 4 D# 1 1 1 1 0 0 0 0 0 0 0 – Data 0 0 A[2:0] 0 0 A[6:3] 0 0 A[9:7] 0 0 A[10] 0 0 A[15:11] 1 0 BA[2:0] 1 0 ODT 0 1 WE# 0 D CAS# ACT 1 RAS# Command 0 CS# Cycle Number SubLoop CKE CK, CK# Table 9: IDD0 Measurement Loop Repeat cycles 1 through 4 until nRAS - 1; tr
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8Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications – I DD Specifications and Conditions 0 0 0 – 0 0 0 0 – 2 D 1 0 0 0 0 0 0 0 0 0 0 – 3 D# 1 1 1 1 0 0 0 0 0 0 0 – 4 D# 1 1 1 1 0 0 0 0 0 0 0 – Data2 A[2:0] 0 0 A[6:3] 0 0 A[9:7] 0 0 A[10] 0 0 A[15:11] 1 0 BA[2:0] 1 0 ODT 0 1 WE# 0 D CAS# ACT 1 RAS# Command 0 CS# Cycle Number Sub-Loop CKE CK, CK# Table 10: IDD1 Measurement Loop Repeat cycles 1 through 4 until nRCD - 1;
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8Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications – I DD Specifications and Conditions Table 11: IDD Measurement Conditions for Power-Down Currents Name IDD2P0 Precharge Power-Down Current (Slow Exit)1 IDD2P1 Precharge Power-Down Current (Fast Exit)1 IDD2Q Precharge Quiet Standby Current IDD3P Active Power-Down Current N/A N/A N/A N/A Timing pattern CKE External clock tCK LOW LOW HIGH LOW Toggling Toggling Toggling Toggling tCK tRC (MIN) IDD N/A tCK (MIN) IDD N/A tCK (MIN) IDD
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8Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications – I DD Specifications and Conditions Static HIGH Toggling Command CS# RAS# CAS# WE# ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] Data 0 Cycle Number Sub-Loop CKE CK, CK# Table 12: IDD2N and IDD3N Measurement Loop 0 D 1 0 0 0 0 0 0 0 0 0 0 – 1 D 1 0 0 0 0 0 0 0 0 0 0 – 2 D# 1 1 1 1 0 0 0 0 0 F 0 – 3 D# 1 1 1 1 0 0 0 0 0 F 0 – 1 4–7 Repeat sub-loop 0, use BA[2:0] = 1 2 8–
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8Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications – I DD Specifications and Conditions A[2:0] Data3 0 0 0 0 0 0 0 00000000 0 0 0 0 0 0 0 0 – 2 D# 1 1 1 1 0 0 0 0 0 0 0 – 3 D# 1 1 1 1 0 0 0 0 0 0 0 – 4 RD 0 1 0 1 0 0 0 0 0 F 0 00110011 5 D 1 0 0 0 0 0 0 0 0 F 0 – 6 D# 1 1 1 1 0 0 0 0 0 F 0 – 7 D# 1 1 1 1 0 0 0 0 0 F 0 – 1 8–15 Repeat sub-loop 0, use BA[2:0] = 1 2 16–23 Repeat sub-loop 0, use BA[2
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8Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications – I DD Specifications and Conditions A[2:0] Data4 1 0 0 0 0 0 0 00000000 0 1 0 0 0 0 0 0 – 2 D# 1 1 1 1 1 0 0 0 0 0 0 – 3 D# 1 1 1 1 1 0 0 0 0 0 0 – 4 WR 0 1 0 0 1 0 0 0 0 F 0 00110011 5 D 1 0 0 0 1 0 0 0 0 F 0 – 6 D# 1 1 1 1 1 0 0 0 0 F 0 – 7 D# 1 1 1 1 1 0 0 0 0 F 0 – 1 8–15 Repeat sub-loop 0, use BA[2:0] = 1 2 16–23 Repeat sub-loop 0, use BA[2
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8Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications – I DD Specifications and Conditions 0 0 0 – 0 0 0 0 – 2 D 1 0 0 0 0 0 0 0 0 0 0 – 3 D# 1 1 1 1 0 0 0 0 0 F 0 – 4 D# 1 1 1 1 0 0 0 0 0 F 0 – Static HIGH Toggling 1a 1b 5–8 Repeat sub-loop 1a, use BA[2:0] = 1 1c 9–12 Repeat sub-loop 1a, use BA[2:0] = 2 1d 13–16 Repeat sub-loop 1a, use BA[2:0] = 3 1e 17–20 Repeat sub-loop 1a, use BA[2:0] = 4 1f 21–24 Repeat sub-loop 1a, use BA[2:0] = 5
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8Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications – I DD Specifications and Conditions Table 17: IDD Measurement Conditions for IDD6, IDD6ET, and IDD8 IDD Test CKE External clock IDD6: Self Refresh Current Normal Temperature Range TC = 0°C to +85°C IDD6ET: Self Refresh Current Extended Temperature Range TC = 0°C to +95°C IDD8: Reset2 LOW LOW Midlevel Off, CK and CK# = LOW Off, CK and CK# = LOW Midlevel tCK N/A N/A N/A tRC N/A N/A N/A tRAS N/A N/A N/A tRCD N/A N/A N/A tRRD N
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8Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications – I DD Specifications and Conditions Command CS# RAS# CAS# WE# ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] Data3 0 Cycle Number Sub-Loop CKE CK, CK# Table 18: IDD7 Measurement Loop 0 ACT 0 0 1 1 0 0 0 0 0 0 0 – 1 RDA 0 1 0 1 0 0 0 1 0 0 0 00000000 2 D 1 0 0 0 0 0 0 0 0 0 0 – 3 1 Static HIGH nRRD ACT 0 0 1 1 0 1 0 0 0 F 0 – nRRD + 1 RDA 0 1 0 1 0 1 0 1 0 F 0 0
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8Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications – I DD Specifications and Conditions 3 × nFAW + 4 × nRRD + 1 Notes: 1. 2. 3. 4.
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8Gb: x4, x8, x16 DDR3L SDRAM Electrical Characteristics – 1.35V IDD Specifications Electrical Characteristics – 1.
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8Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications – DC and AC Electrical Specifications – DC and AC DC Operating Conditions Table 20: DDR3L 1.35V DC Electrical Characteristics and Operating Conditions All voltages are referenced to VSS Parameter/Condition Symbol Min Nom Max Unit Notes Supply voltage VDD 1.283 1.35 1.45 V 1–7 I/O supply voltage VDDQ 1.283 1.35 1.45 V 1–7 II –2 – 2 μA IVREF –1 – 1 μA Input leakage current Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤ 1.
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8Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications – DC and AC Input Operating Conditions Table 21: DDR3L 1.35V DC Electrical Characteristics and Input Conditions All voltages are referenced to VSS Parameter/Condition Symbol Min Nom Max Unit VIN low; DC/commands/address busses VIL VSS N/A See Table 22 V VIN high; DC/commands/address busses VIH See Table 22 N/A VDD V Notes Input reference voltage command/address bus VREFCA(DC) 0.49 × VDD 0.5 × VDD 0.
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8Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications – DC and AC Table 22: DDR3L 1.
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8Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications – DC and AC Table 23: DDR3L 1.
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8Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications – DC and AC Figure 11: DDR3L 1.35V Input Signal VIL and VIH levels with ringback VDD + 0.4V Narrow pulse width VDD Minimum VIL and VIH levels VIH MIN(AC) VIH MIN(DC) VIH(AC) VIH(DC) VIL MIN(DC) VIL MIN(AC) VDDQ VREF + 125/135/160mV VIH(AC) VREF + 90mV VIH(DC) VREF DC MAX + 1% .51 x VDD VREF = VDD/2 .
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8Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications – DC and AC DDR3L 1.35V AC Overshoot/Undershoot Specification Table 24: DDR3L Control and Address Pins Parameter DDR3L-800 DRR3L-1066 DDR3L-1333 DDR3L-1600 DDR3L-1866 DDR3L-2133 Maximum peak amplitude allowed for overshoot area (see Figure 12) 0.4V 0.4V 0.4V 0.4V 0.4V 0.4V Maximum peak amplitude allowed for undershoot area (see Figure 13) 0.4V 0.4V 0.4V 0.4V 0.4V 0.4V Maximum overshoot area above VDD (see Figure 12) 0.67 V/ns 0.
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8Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications – DC and AC Figure 13: Undershoot VSS/VSSQ Volts (V) Undershoot area Maximum amplitude Time (ns) Figure 14: VIX for Differential Signals VDD, VDDQ VDD, VDDQ CK#, DQS# CK#, DQS# X VIX VIX VDD/2, VDDQ/2 X X VDD/2, VDDQ/2 VIX X VIX CK, DQS CK, DQS VSS, VSSQ VSS, VSSQ Figure 15: Single-Ended Requirements for Differential Signals VDD or VDDQ VSEH,min VDD/2 or VDDQ/2 VSEH CK or DQS VSEL,max VSEL VSS or VSSQ Rev.2.
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8Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications – DC and AC Figure 16: Definition of Differential AC-Swing and tDVAC tDVAC VIH,diff(AC)min VIH,diff,min CK - CK# DQS - DQS# 0.0 VIL,diff,max VIL,diff(AC)max tDVAC Half cycle Table 26: DDR3L 1.35V – Minimum Required Time tDVAC for CK/CK#, DQS/DQS# Differential for AC Ringback DDR3L-800/1066/1333/1600 tDVAC tDVAC DDR3L-1866/2133 tDVAC tDVAC tDVAC Slew Rate (V/ns) at 320mV (ps) at 270mV (ps) at 270mV (ps) at 250mV (ps) at 260mV (ps) >4.
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8Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications – DC and AC DDR3L 1.35V Slew Rate Definitions for Single-Ended Input Signals Setup (tIS and tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V REF and the first crossing of V IH(AC)min. Setup (tIS and tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of V REF and the first crossing of V IL(AC)max.
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8Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications – DC and AC Figure 17: Nominal Slew Rate Definition for Single-Ended Input Signals ΔTRSse Setup Single-ended input voltage (DQ, CMD, ADDR) VIH(AC)min VIH(DC)min VREFDQ or VREFCA VIL(DC)max VIL(AC)max ΔTFSse ΔTRHse Hold Single-ended input voltage (DQ, CMD, ADDR) VIH(AC)min VIH(DC)min VREFDQ or VREFCA VIL(DC)max VIL(AC)max ΔTFHse Rev 2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc.
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8Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications – DC and AC DDR3L 1.35V Slew Rate Definitions for Differential Input Signals Input slew rate for differential signals (CK, CK# and DQS, DQS#) are defined and measured, as shown in Table 28 and Figure 18. The nominal slew rate for a rising signal is defined as the slew rate between V IL,diff,max and V IH,diff,min. The nominal slew rate for a falling signal is defined as the slew rate between V IH,diff,min and V IL,diff,max. Table 28: DDR3L 1.
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8Gb: x4, x8, x16 DDR3L SDRAM ODT Characteristics ODT Characteristics The ODT effective resistance RTT is defined by MR1[9, 6, and 2]. ODT is applied to the DQ, DM, DQS, DQS#, and TDQS, TDQS# balls (x8 devices only). The ODT target values and a functional representation are listed in Table 29 and Table 30 (page 51).
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8Gb: x4, x8, x16 DDR3L SDRAM ODT Characteristics 1.35V ODT Resistors Table 30 provides an overview of the ODT DC electrical characteristics.
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8Gb: x4, x8, x16 DDR3L SDRAM ODT Characteristics Table 30: 1.35V RTT Effective Impedance (Continued) MR1 [9, 6, 2] RTT Resistor VOUT Min Nom Max Units 1, 0, 0 Ω RTT,20PD40 0.2 × VDDQ 0.6 1.0 1.15 RZQ/6 0.5 × VDDQ 0.9 1.0 1.15 RZQ/6 0.8 × VDDQ 0.9 1.0 1.45 RZQ/6 0.2 × VDDQ 0.9 1.0 1.45 RZQ/6 0.5 × VDDQ 0.9 1.0 1.15 RZQ/6 0.8 × VDDQ 0.6 1.0 1.15 RZQ/6 VIL(AC) to VIH(AC) 0.9 1.0 1.
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8Gb: x4, x8, x16 DDR3L SDRAM ODT Characteristics Figure 20: ODT Timing Reference Load DUT CK, CK# VREF VDDQ/2 RTT = 25Ω DQ, DM DQS, DQS# TDQS, TDQS# ZQ VTT = VSSQ Timing reference point RZQ = 240Ω VSSQ Table 33: ODT Timing Definitions Symbol Begin Point Definition End Point Definition Figure tAON Rising edge of CK – CK# defined by the end point of ODTLon Extrapolated point at VSSQ Figure 21 (page 54) tAOF Rising edge of CK – CK# defined by the end point of ODTLoff Extrapolated point at VRTT,n
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8Gb: x4, x8, x16 DDR3L SDRAM ODT Characteristics Figure 21: tAON and tAOF Definitions tAON tAOF Begin point: Rising edge of CK - CK# defined by the end point of ODTLoff Begin point: Rising edge of CK - CK# defined by the end point of ODTLon CK CK VDDQ/2 CK# CK# tAON tAOF End point: Extrapolated point at VRTT,nom TSW2 TSW1 TSW1 DQ, DM DQS, DQS# TDQS, TDQS# VSW2 TSW1 VSW2 VSW1 VSW1 VSSQ VRTT,nom VSSQ End point: Extrapolated point at VSSQ Figure 22: tAONPD and tAOFPD Definitions tAONPD Begin
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8Gb: x4, x8, x16 DDR3L SDRAM ODT Characteristics Figure 23: tADC Definition Begin point: Rising edge of CK - CK# defined by the end point of ODTLcnw Begin point: Rising edge of CK - CK# defined by the end point of ODTLcwn4 or ODTLcwn8 CK VDDQ/2 CK# tADC VRTT,nom DQ, DM DQS, DQS# TDQS, TDQS# End point: Extrapolated point at VRTT,nom tADC VRTT,nom TSW21 TSW11 VSW2 VSW1 TSW22 TSW12 VRTT(WR) End point: Extrapolated point at VRTT(WR) VSSQ Rev 2.0 June 2016 © 2015 Alliance Memory, Inc.
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8Gb: x4, x8, x16 DDR3L SDRAM Output Driver Impedance Output Driver Impedance The output driver impedance is selected by MR1[5,1] during initialization. The selected value is able to maintain the tight tolerances specified if proper ZQ calibration is performed. Output specifications refer to the default output driver unless specifically stated otherwise. A functional representation of the output buffer is shown below.
PAGE 58
8Gb: x4, x8, x16 DDR3L SDRAM Output Driver Impedance 34 Ohm Output Driver Impedance The 34Ω driver (MR1[5, 1] = 01) is the default driver. Unless otherwise stated, all timings and specifications listed herein apply to the 34Ω driver only. Its impedance RON is defined by the value of the external reference resistor RZQ as follows: RON34 = RZQ/7 (with nominal RZQ = 240Ω ±1%) and is actually 34.
PAGE 59
8Gb: x4, x8, x16 DDR3L SDRAM Output Driver Impedance DDR3L 34 Ohm Driver Using Table 36, the 34Ω driver’s current range has been calculated and summarized in Table 37 (page 58) V DD = 1.35V, Table 38 for V DD = 1.45V, and Table 39 (page 59) for VDD = 1.283V.
PAGE 60
8Gb: x4, x8, x16 DDR3L SDRAM Output Driver Impedance Table 39: DDR3L 34 Ohm Driver IOH/IOL Characteristics: VDD = VDDQ = DDR3L@1.283 MR1[5,1] RON Resistor VOUT Max Nom Min Unit 0, 1 Ω RON34(PD) IOL @ 0.2 × VDDQ 12.6 7.5 6.7 mA IOL @ 0.5 × VDDQ 21.0 18.7 16.8 mA IOL @ 0.8 × VDDQ 33.6 29.9 21.2 mA RON34(PU) IOH @ 0.2 × VDDQ 33.6 29.9 21.2 mA IOH @ 0.5 × VDDQ 21.0 18.7 16.8 mA IOH @ 0.8 × VDDQ 12.6 7.5 6.
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8Gb: x4, x8, x16 DDR3L SDRAM Output Driver Impedance DDR3L Alternative 40 Ohm Driver Table 42: DDR3L 40 Ohm Driver Impedance Characteristics MR1 [5, 1] RON Resistor VOUT Min Nom Max Units 0, 0 Ω RON,40PD 0.2 × VDDQ 0.6 1.0 1.15 RZQ/6 0.5 × VDDQ 0.9 1.0 1.15 RZQ/6 0.8 × VDDQ 0.9 1.0 1.45 RZQ/6 0.2 × VDDQ 0.9 1.0 1.45 RZQ/6 0.5 × VDDQ 0.9 1.0 1.15 RZQ/6 0.8 × VDDQ 0.6 1.0 1.
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8Gb: x4, x8, x16 DDR3L SDRAM Output Driver Impedance Table 44: 40 Ohm Output Driver Voltage and Temperature Sensitivity Change Min Max Unit dRONdTM 0 1.5 %/°C dRONdVM 0 0.15 %/mV dRONdTL 0 1.5 %/°C dRONdVL 0 0.15 %/mV dRONdTH 0 1.5 %/°C dRONdVH 0 0.15 %/mV Rev 2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc. reserves the right to change products or specification without notice 61 Alliance Memory Inc.
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8Gb: x4, x8, x16 DDR3L SDRAM Output Characteristics and Operating Conditions Output Characteristics and Operating Conditions Table 45: DDR3L Single-Ended Output Driver Characteristics All voltages are referenced to VSS Parameter/Condition Output leakage current: DQ are disabled; 0V ≤ VOUT ≤ VDDQ; ODT is disabled; ODT is HIGH Output slew rate: Single-ended; For rising and falling edges, measure between VOL(AC) = VREF - 0.09 × VDDQ and VOH(AC) = VREF + 0.
PAGE 64
8Gb: x4, x8, x16 DDR3L SDRAM Output Characteristics and Operating Conditions Figure 25: DQ Output Signal MAX output VOH(AC) VOL(AC) MIN output Table 46: DDR3L Differential Output Driver Characteristics All voltages are referenced to VSS Parameter/Condition Output leakage current: DQ are disabled; 0V ≤ VOUT ≤ VDDQ; ODT is disabled; ODT is HIGH DDR3L Output slew rate: Differential; For rising and falling edges, measure between VOL,diff(AC) = –0.18 × VDDQ and VOH,diff(AC) = 0.
PAGE 65
8Gb: x4, x8, x16 DDR3L SDRAM Output Characteristics and Operating Conditions Table 47: DDR3L Differential Output Driver Characteristics VOX(AC) All voltages are referenced to VSS Parameter/ Condition Output differential crosspoint voltage Parameter/ Condition Output differential crosspoint voltage DDR3L- 800/1066/1333 DQS/DQS# Differential Slew Rate Symbol 3.
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8Gb: x4, x8, x16 DDR3L SDRAM Output Characteristics and Operating Conditions Reference Output Load Figure 27 (page 65) represents the effective reference load of 25Ω used in defining the relevant device AC timing parameters (except ODT reference timing) as well as the output slew rate measurements. It is not intended to be a precise representation of a particular system environment or a depiction of the actual load presented by a production tester.
PAGE 67
8Gb: x4, x8, x16 DDR3L SDRAM Output Characteristics and Operating Conditions Figure 28: Nominal Slew Rate Definition for Single-Ended Output Signals ΔTRse VOH(AC) VTT VOL(AC) ΔTFse Rev 2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc. reserves the right to change products or specification without notice 66 Alliance Memory Inc.
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8Gb: x4, x8, x16 DDR3L SDRAM Output Characteristics and Operating Conditions Slew Rate Definitions for Differential Output Signals The differential output driver is summarized in Table 46 (page 63). With the reference load for timing measurements, the output slew rate for falling and rising edges is defined and measured between V OL(AC) and V OH(AC) for differential signals.
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8Gb: x4, x8, x16 DDR3L SDRAM Speed Bin Tables Speed Bin Tables Table 50: DDR3L-1066 Speed Bins DDR3L-1066 Speed Bin -18E -18 CL-tRCD-tRP 7-7-7 8-8-8 Parameter Symbol Min Max Min Max Unit tAA 13.125 – 15 – ns tRCD 13.125 – 15 – ns PRECHARGE command period tRP 13.125 – 15 – ns ACTIVATE-to-ACTIVATE or REFRESH command period tRC 50.625 – 52.5 – ns tRAS 37.5 9 x tREFI 37.5 9 x tREFI ns 1 3.0 3.3 3.0 3.
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8Gb: x4, x8, x16 DDR3L SDRAM Speed Bin Tables Table 51: DDR3L-1333 Speed Bins DDR3L-1333 Speed Bin -15E1 -152 CL-tRCD-tRP 9-9-9 10-10-10 Parameter Symbol Min Max Min Max Unit tAA 13.5 – 15 – ns tRCD 13.5 – 15 – ns PRECHARGE command period tRP 13.5 – 15 – ns ACTIVATE-to-ACTIVATE or REFRESH command period tRC 49.5 – 51 – ns tRAS 36 9 x tREFI 36 9 x tREFI ns 3 3.0 3.3 3.0 3.
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8Gb: x4, x8, x16 DDR3L SDRAM Speed Bin Tables Table 52: DDR3L-1600 Speed Bins -121 DDR3L-1600 Speed Bin CL-tRCD-tRP 11-11-11 Parameter Symbol Min Max Unit tAA 13.75 – ns tRCD 13.75 – ns PRECHARGE command period tRP 13.75 – ns ACTIVATE-to-ACTIVATE or REFRESH command period tRC 48.75 – ns tRAS 35 9 x tREFI ns 2 3.0 3.
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8Gb: x4, x8, x16 DDR3L SDRAM Speed Bin Tables Table 53: DDR3L-1866 Speed Bins -101 DDR3L-1866 Speed Bin CL-tRCD-tRP 13-13-13 Parameter Symbol Min Max tAA 13.91 20 tRCD 13.91 – ns PRECHARGE command period tRP 13.91 – ns ACTIVATE-to-ACTIVATE or REFRESH command period tRC 47.91 – ns tRAS 34 9 x tREFI ns 2 3.0 3.
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8Gb: x4, x8, x16 DDR3L SDRAM Speed Bin Tables Table 54: DDR3L-2133 Speed Bins -091 DDR3L-2133 Speed Bin CL-tRCD-tRP 14-14-14 Parameter Symbol Min Max tAA 13.09 20 tRCD 13.09 – ns PRECHARGE command period tRP 13.09 – ns ACTIVATE-to-ACTIVATE or REFRESH command period tRC 46.09 – ns tRAS 33 9 x tREFI ns 2 3.0 3.
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TC ≤ 85°C Rev 2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc. reserves the right to change products or specification without notice 73 –147 –175 –194 –209 –222 –232 –241 –249 –257 –263 –269 tERR3per tERR4per tERR5per tERR6per tERR7per tERR8per tERR9per tERR10per tERR11per tERR12per tERRnper 3 cycles 4 cycles 5 cycles 6 cycles 7 cycles 8 cycles 9 cycles 10 cycles 11 cycles 12 cycles n = 13, 14 . . . 49, 50 cycles 180 tERR2per 200 tJITcc,lck DLL locking 0.
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Rev 2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc. reserves the right to change products or specification without notice – 0.38 tDQSQ tQH 74 – – – – – – – 490 200 110 250 90 200 40 – –0.25 0.45 0.45 tDQSS tDQSL tDQSH DQ High-Z time from CK, CK# DQS, DQS# rising to CK, CK# rising DQS, DQS# differential input low pulse width DQS, DQS# differential input high pulse width 400 400 – 200 – –600 0.38 – 0.9 0.3 –400 1 0.38 0.
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0.9 0.3 tRPST DQS, DQS# differential READ preamble DQS, DQS# differential READ postamble Rev 2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc. reserves the right to change products or specification without notice 75 VREF @ 1 V/ns 0.3 0.9 – Note 27 Note 24 300 300 Max – – – – – – 620 240 150 340 205 240 80 512 MIN = greater of 4CK or 7.5ns; MAX = N/A MIN = greater of 4CK or 7.
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Rev 2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc. reserves the right to change products or specification without notice 78 Write leveling setup from rising CK, CK# crossing to rising DQS, DQS# crossing DQS, DQS# delay First DQS, DQS# rising edge RTT dynamic change skew ODTLcwn8 RTT(WR)-to-RTT,nom change skew - BL8 0.7 0.3 40 25 325 tWLDQSEN tWLS – – – 245 25 40 Write Leveling Timing 0.3 – – – 0.7 195 25 40 0.
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Min 325 0 0 Symbol tWLH tWLO tWLOE Write leveling output delay Write leveling output error 2 9 – Max DDR3L-800 Write leveling hold from rising DQS, DQS# crossing to rising CK, CK# crossing Parameter Notes 1–8 apply to the entire table 0 0 245 Min 2 9 – Max DDR3L-1066 Table 55: Electrical Characteristics and AC Operating Conditions (Continued) 0 0 195 Min 2 9 – Max DDR3L-1333 0 0 165 Min 2 7.
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8Gb: x4, x8, x16 DDR3L SDRAM Electrical Characteristics and AC Operating Conditions Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. AC timing parameters are valid from specified TC MIN to TC MAX values. All voltages are referenced to VSS. Output timings are only valid for RON34 output buffer selection. The unit tCK (AVG) represents the actual tCK (AVG) of the input clock under operation.
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8Gb: x4, x8, x16 DDR3L SDRAM Electrical Characteristics and AC Operating Conditions 19. These parameters are measured from a data signal (DM, DQ0, DQ1, and so forth) transition edge to its respective data strobe signal (DQS, DQS#) crossing. 20. The setup and hold times are listed converting the base specification values (to which derating tables apply) to VREF when the slew rate is 1 V/ns. These values, with a slew rate of 1 V/ns, are for reference only. 21.
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8Gb: x4, x8, x16 DDR3L SDRAM Electrical Characteristics and AC Operating Conditions 37. Although CKE is allowed to be registered LOW after a REFRESH command when tREFPDEN (MIN) is satisfied, there are cases where additional time such as tXPDLL (MIN) is required. 38. ODT turn-on time MIN is when the device leaves High-Z and ODT resistance begins to turn on. ODT turn-on time maximum is when the ODT resistance is fully on. The ODT reference load is shown in Figure 20 (page 53).
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Rev 2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc. reserves the right to change products or specification without notice 83 120 100 tJITcc tJITcc,lck DLL locking 0.43 0.43 3900 7800 Max – – 50 60 tCK DDR3L-2133 3900 7800 Max –40 –50 0.47 0.43 0.43 120 100 – – 40 50 0.53 0.53 range allowed ns 0.47 tCK 8 8 Min MIN = (AVG) MIN + tJITper MIN; MAX = tCK (AVG) MAX + tJITper MAX ps 0.53 0.
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Rev 2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc. reserves the right to change products or specification without notice tERR9per tERR10per 8 cycles 9 cycles 10 cycles 11 cycles 84 0.38 – –0.27 0.45 tDQSS tDQSL DQ High-Z time from CK, CK# DQS, DQS# rising to CK, CK# rising DQS, DQS# differential input low pulse width 195 195 – 85 – – – – – 0.55 0.
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– 2Gb – 4Gb – 8Gb tRFC tRFC tRFC Max Min Self Refresh Timing 64 (1X) MIN = 350; MAX = 70,200 MIN = 260; MAX = 70,200 MIN = 160; MAX = 70,200 Rev 2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc.
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MIN = WL + 2 + tWR/tCK (AVG) MIN = WL + 4 + WR + 1 tWRPDEN tWRPDEN tWRAP- BL8 (OTF, MRS) BC4OTF BC4MRS WRITE command to power-down entry Rev 2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc. reserves the right to change products or specification without notice 88 ODTH8 ODT HIGH time with WRITE command and BL8 MIN = 6; MAX = N/A MIN = 2; MAX = 8.5 tAOFPD Asynchronous RTT turn-off delay (power-down with DLL off) 0.3 –180 MIN = 2; MAX = 8.5 0.
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0.3 40 25 140 140 tWLS tWLH Write leveling setup from rising CK, CK# crossing to rising DQS, DQS# crossing Write leveling hold from rising DQS, DQS# crossing to rising CK, CK# crossing Rev 2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc. reserves the right to change products or specification without notice 89 0 0 tWLO tWLOE Write leveling output delay Write leveling output error Min 0.7 – 2 7.5 – – – 25 40 0.
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8Gb: x4, x8, x16 DDR3L SDRAM Electrical Characteristics and AC Operating Conditions Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. AC timing parameters are valid from specified TC MIN to TC MAX values. All voltages are referenced to VSS. Output timings are only valid for RON34 output buffer selection. The unit tCK (AVG) represents the actual tCK (AVG) of the input clock under operation.
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8Gb: x4, x8, x16 DDR3L SDRAM Electrical Characteristics and AC Operating Conditions 19. These parameters are measured from a data signal (DM, DQ0, DQ1, and so forth) transition edge to its respective data strobe signal (DQS, DQS#) crossing. 20. The setup and hold times are listed converting the base specification values (to which derating tables apply) to VREF when the slew rate is 1 V/ns (DQs are at 2V/ns for DDR3-1866 and DDR3-2133).
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8Gb: x4, x8, x16 DDR3L SDRAM Electrical Characteristics and AC Operating Conditions 36. The refresh period is 64ms when TC is less than or equal to 85°C. This equates to an average refresh rate of 7.8125μs. However, nine REFRESH commands should be asserted at least once every 70.3μs. When TC is greater than 85°C, the refresh period is 32ms. 37.
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8Gb: x4, x8, x16 DDR3L SDRAM Command and Address Setup, Hold, and Derating Command and Address Setup, Hold, and Derating The total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS (base) and tIH (base) values (see Table 57; values come from the Electrical Characteristics and AC Operating Conditions table) to the ΔtIS and ΔtIH derating values (see Table 58 (page 94), Table 59 (page 94) or Table 60 (page 94)) respectively.
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8Gb: x4, x8, x16 DDR3L SDRAM Command and Address Setup, Hold, and Derating Table 58: DDR3L-800/1066 Derating Values tIS/tIH – AC160/DC90-Based ΔtIS, ΔtIH Derating (ps) – AC/DC-Based CMD/ADDR 4.0 V/ns Slew Rate V/ns ΔtIS ΔtIH CK, CK# Differential Slew Rate 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS 1.2 V/ns ΔtIH ΔtIS 1.0 V/ns ΔtIH ΔtIS ΔtIH 2.0 80 45 80 45 80 45 88 53 96 61 104 69 112 79 120 95 1.
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8Gb: x4, x8, x16 DDR3L SDRAM Command and Address Setup, Hold, and Derating Table 60: DDR3L-1866/2133 Derating Values for tIS/tIH – AC125/DC90-Based (Continued) ΔtIS, ΔtIH Derating (ps) – AC/DC-Based CMD/ADDR 4.0 V/ns Slew Rate V/ns ΔtIS ΔtIH CK, CK# Differential Slew Rate 3.0 V/ns ΔtIS ΔtIH 2.0 V/ns ΔtIS ΔtIH 1.8 V/ns ΔtIS 1.6 V/ns ΔtIH ΔtIS ΔtIH 1.4 V/ns ΔtIS ΔtIH 1.2 V/ns ΔtIS 1.0 V/ns ΔtIH ΔtIS ΔtIH 0.9 3 –3 3 –3 3 –3 11 5 19 13 27 21 35 31 43 47 0.
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8Gb: x4, x8, x16 DDR3L SDRAM Command and Address Setup, Hold, and Derating Figure 30: Nominal Slew Rate and tVAC for tIS (Command and Address – Clock) tIS tIH tIS tIH CK CK# DQS# DQS VDDQ tVAC VIH(AC)min VREF to AC region VIH(DC)min Nominal slew rate VREF(DC) Nominal slew rate VIL(DC)max VREF to AC region VIL(DC)max tVAC VSS ΔTF Setup slew rate falling signal = Note: ΔTR VREF(DC) - VIL(AC)max Setup slew rate rising signal = ΔTF VIH(AC)min - VREF(DC) ΔTR 1.
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8Gb: x4, x8, x16 DDR3L SDRAM Command and Address Setup, Hold, and Derating Figure 31: Nominal Slew Rate for tIH (Command and Address – Clock) tIS tIS tIH tIH CK CK# DQS# DQS VDDQ VIH(AC)min VIH(DC)min Nominal slew rate DC to VREF region VREF(DC) Nominal slew rate DC to VREF region VIL(DC)max VIL(AC)max VSS ΔTF ΔTR VREF(DC) - VIL(DC)max Hold slew rate rising signal = ΔTR Note: VIH(DC)min - VREF(DC) Hold slew rate falling signal = ΔTF 1.
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8Gb: x4, x8, x16 DDR3L SDRAM Command and Address Setup, Hold, and Derating Figure 32: Tangent Line for tIS (Command and Address – Clock) tIS tIS tIH tIH CK CK# DQS# DQS VDDQ Nominal line tVAC VIH(AC)min VREF to AC region VIH(DC)min Tangent line VREF(DC) Tangent line VIL(DC)max VREF to AC region VIL(DC)max Nominal line tVAC ΔTR VSS Tangent line (VIH(DC)min - VREF(DC)) Setup slew rate rising signal = ΔTR ΔTF Note: Tangent line (VREF(DC) - VIL(AC)max) Setup slew rate falling signal = ΔTF 1.
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8Gb: x4, x8, x16 DDR3L SDRAM Command and Address Setup, Hold, and Derating Figure 33: Tangent Line for tIH (Command and Address – Clock) tIS tIH tIS tIH CK CK# DQS# DQS VDDQ VIH(AC)min Nominal line VIH(DC)min DC to VREF region Tangen t line VREF(DC) DC to VREF region Tangen t line Nominal line VIL( DC)max VIL( AC)max VSS ΔTR ΔTR Tangent line (VREF(DC) - VIL(DC)max) Hold slew rate rising signal = ΔTR Tangent line (VIH(DC)min - VREF(DC)) Hold slew rate falling signal = ΔTF Note: 1.
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8Gb: x4, x8, x16 DDR3L SDRAM Data Setup, Hold, and Derating Data Setup, Hold, and Derating The total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet tDS (base) and tDH (base) values (see Table 62 (page 100); values come from the Electrical Characteristics and AC Operating Conditions table) to the ΔtDS and ΔtDH derating values (see Table 63 (page 101), Table 64 (page 101), or Table 65 (page 102)) respectively. Example: tDS (total setup time) = tDS (base) + ΔtDS.
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8Gb: x4, x8, x16 DDR3L SDRAM Data Setup, Hold, and Derating Table 63: DDR3L Derating Values for tDS/tDH – AC160/DC90-Based ΔtDS, ΔtDH Derating (ps) – AC/DC-Based DQS, DQS# Differential Slew Rate DQ Slew Rate V/ns 4.0 V/ns ΔtDS ΔtDH 3.0 V/ns ΔtDS 2.0 V/ns ΔtDH ΔtDS ΔtDH 1.8 V/ns ΔtDS ΔtDH 1.6 V/ns ΔtDS ΔtDH 1.4 V/ns ΔtDS ΔtDH 1.2 V/ns ΔtDS ΔtDH 1.0 V/ns ΔtDS ΔtDH 2.0 80 45 80 45 80 45 1.5 53 30 53 30 53 30 61 38 1.
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28 22 3.5 3.0 Rev 2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc. reserves the right to change products or specification without notice 102 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.5 2.0 2.5 33 4.0 15 19 23 Δ tDH Δ tDS 8.0 V/ns DQ Slew Rate V/ns 13 22 28 33 tDS Δ 9 15 19 23 tDH Δ 7.0 V/ns 0 13 22 28 33 tDS Δ 0 9 15 19 23 tDH Δ 6.0 V/ns –22 0 13 22 28 tDS Δ –15 0 9 15 19 tDH Δ 5.
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8Gb: x4, x8, x16 DDR3L SDRAM Data Setup, Hold, and Derating Table 66: DDR3L Minimum Required Time tVAC Above VIH(AC) (Below VIL(AC)) for Valid DQ Transition Slew Rate (V/ns) DDR3L-800/1066 160mV (ps) min DDR3L-800/1066/1333 135mV (ps) min DDR3L-1866/2133 130mV (ps) min >2.0 165 113 95 2.0 165 113 95 1.5 138 90 73 1.0 85 45 30 0.9 67 30 16 0.8 45 11 Note 1 0.7 16 Note 1 – 0.6 Note 1 Note 1 – 0.5 Note 1 Note 1 – <0.5 Note 1 Note 1 – Note: 1.
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8Gb: x4, x8, x16 DDR3L SDRAM Data Setup, Hold, and Derating Figure 34: Nominal Slew Rate and tVAC for tDS (DQ – Strobe) CK CK# DQS# DQS tDS tDH tDS tDH VDDQ tVAC VIH(AC)min VREF to AC region VIH(DC)min Nominal slew rate VREF(DC) Nominal slew rate VIL(DC)max VREF to AC region VIL(AC)max tVAC VSS ΔTF Setup slew rate = falling signal Note: ΔTR VIH(AC)min - VREF(DC) Setup slew rate = rising signal ΔTR VREF(DC) - VIL(AC)max ΔTF 1. The clock and the strobe are drawn on different time scales.
PAGE 106
8Gb: x4, x8, x16 DDR3L SDRAM Data Setup, Hold, and Derating Figure 35: Nominal Slew Rate for tDH (DQ – Strobe) CK CK# DQS# DQS tDS tDH tDS tDH VDDQ VIH(AC)min VIH(DC)min Nominal slew rate DC to VREF region VREF(DC) Nominal slew rate DC to VREF region VIL(DC)max VIL(AC)max VSS ΔTR VREF(DC) - VIL(DC)max Hold slew rate rising signal = ΔTR Note: ΔTF VIL(DC)min - VREF(DC) Hold slew rate falling signal = ΔTF 1. The clock and the strobe are drawn on different time scales. Rev 2.
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8Gb: x4, x8, x16 DDR3L SDRAM Data Setup, Hold, and Derating Figure 36: Tangent Line for tDS (DQ – Strobe) CK CK# DQS# DQS tDS tDH tDS tDH VDDQ Nominal line tVAC VIH(AC)min VREF to AC region VIH(DC)min Tangent line VREF(DC) Tangent line VIL(DC)max VREF to AC region VIL(AC)max Nominal line ΔTR tVAC VSS Setup slew rate Tangent line (VIH(AC)min - VREF(DC)) rising signal = ΔTR ΔTF Note: Setup slew rate Tangent line (VREF(DC) - VIL(AC)max) falling signal = ΔTF 1.
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8Gb: x4, x8, x16 DDR3L SDRAM Data Setup, Hold, and Derating Figure 37: Tangent Line for tDH (DQ – Strobe) CK CK# DQS# DQS tDS tDH tDS tDH VDDQ VIH(AC)min Nominal line VIH(DC)min DC to VREF region Tangent line VREF(DC) DC to VREF region Tangent line Nominal line VIL(DC)max VIL(AC)max VSS ΔTR Note: ΔTF Hold slew rate rising signal = Tangent line (VREF(DC) - VIL(DC)max) Hold slew rate falling signal = Tangent line (VIH(DC)min - VREF(DC)) ΔTR ΔTF 1.
PAGE 109
8Gb: x4, x8, x16 DDR3L SDRAM Commands – Truth Tables Commands – Truth Tables Table 67: Truth Table – Command Notes 1–5 apply to the entire table CKE Symbol Prev.
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8Gb: x4, x8, x16 DDR3L SDRAM Commands – Truth Tables 2. RESET# is enabled LOW and used only for asynchronous reset. Thus, RESET# must be held HIGH during any normal operation. 3. The state of ODT does not affect the states described in this table. 4. Operations apply to the bank defined by the bank address. For MRS, BA selects one of four mode registers. 5. “V” means “H” or “L” (a defined logic level), and “X” means “Don’t Care.” 6. See Table 68 (page 110) for additional information on CKE transition. 7.
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8Gb: x4, x8, x16 DDR3L SDRAM Commands – Truth Tables Table 68: Truth Table – CKE Notes 1–2 apply to the entire table; see Table 67 (page 108) for additional command details CKE Current State3 Power-down Previous Cycle4 Present Cycle4 Command5 (n - 1) (n) (RAS#, CAS#, WE#, CS#) Action5 L L “Don’t Care” Maintain power-down L H DES or NOP Power-down exit Self refresh L L “Don’t Care” Maintain self refresh L H DES or NOP Self refresh exit Bank(s) active H L DES or NOP Active power-dow
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8Gb: x4, x8, x16 DDR3L SDRAM Commands Commands DESELECT The DESELT (DES) command (CS# HIGH) prevents new commands from being executed by the DRAM. Operations already in progress are not affected. NO OPERATION The NO OPERATION (NOP) command (CS# LOW) prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected.
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8Gb: x4, x8, x16 DDR3L SDRAM Commands precharge is not selected, the row will remain open for subsequent accesses. The value on input A12 (if enabled in the mode register) when the READ command is issued determines whether BC4 (chop) or BL8 is used. After a READ command is issued, the READ burst may not be interrupted. Table 69: READ Command Summary CKE Function READ READ with auto precharge Symbol Prev.
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8Gb: x4, x8, x16 DDR3L SDRAM Commands PRECHARGE The PRECHARGE command is used to de-activate the open row in a particular bank or in all banks. The bank(s) are available for a subsequent row access a specified time ( tRP) after the PRECHARGE command is issued, except in the case of concurrent auto precharge.
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8Gb: x4, x8, x16 DDR3L SDRAM Commands Figure 38: Refresh Mode T0 T2 T1 CK# CK tCK T3 tCH T4 Ta1 Valid 5 NOP1 PRE Tb0 Tb1 Valid 5 Valid 5 NOP5 NOP5 Tb2 tCL CKE Command Ta0 NOP1 NOP1 REF NOP5 REF2 Address ACT RA All banks A10 RA One bank BA[2:0] Bank(s)3 BA DQS, DQS#4 DQ4 DM4 tRP tRFC (MIN) tRFC2 Indicates break in time scale Notes: Don’t Care 1. NOP commands are shown for ease of illustration; other valid commands may be possible at these times.
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8Gb: x4, x8, x16 DDR3L SDRAM Commands DLL Disable Mode If the DLL is disabled by the mode register (MR1[0] can be switched during initialization or later), the DRAM is targeted, but not guaranteed, to operate similarly to the normal mode, with a few notable exceptions: • The DRAM supports only one value of CAS latency (CL = 6) and one value of CAS WRITE latency (CWL = 6).
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8Gb: x4, x8, x16 DDR3L SDRAM Commands Figure 39: DLL Enable Mode to DLL Disable Mode T0 T1 Ta0 Ta1 Tb0 Tc0 Td0 Td1 Te0 Te1 Tf0 CK# CK Valid1 CKE MRS2 Command 6 SRE3 NOP SRX4 NOP 7 tCKSRE tMOD tCKSRX8 NOP tXS MRS5 NOP Valid1 tMOD tCKESR ODT9 Valid1 Indicates break in time scale Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. Don’t Care Any valid command. Disable DLL by setting MR1[0] to 1. Enter SELF REFRESH. Exit SELF REFRESH.
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8Gb: x4, x8, x16 DDR3L SDRAM Commands Figure 40: DLL Disable Mode to DLL Enable Mode T0 Ta0 Ta1 Tb0 Tc0 Tc1 Td0 Te0 Tf0 Tg0 Th0 CK# CK CKE Valid tDLLK Command SRE1 NOP SRX2 NOP tCKSRE 7 8 tCKSRX9 MRS3 tXS MRS4 tMRD MRS5 Valid 6 tMRD ODTLoff + 1 × tCK tCKESR ODT10 Indicates break in time scale Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. Don’t Care Enter SELF REFRESH. Exit SELF REFRESH. Wait tXS, then set MR1[0] to 0 to enable DLL. Wait tMRD, then set MR0[8] to 1 to begin DLL RESET.
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8Gb: x4, x8, x16 DDR3L SDRAM Commands Figure 41: DLL Disable tDQSCK T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 Command READ NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP Address Valid CK# CK RL = AL + CL = 6 (CL = 6, AL = 0) CL = 6 DQS, DQS# DLL on DI b DQ BL8 DLL on RL (DLL_DIS) = AL + (CL - 1) = 5 DI b+1 DI b+2 DI b+3 DI b+4 DI b+5 DI b+6 DI b+7 tDQSCK (DLL_DIS) MIN DQS, DQS# DLL off DI b DQ BL8 DLL disable DI b+1 tDQSCK DI b+2 DI b+3 DI b+4 DI b+5 DI b+6 DI b+7 DI b+3 DI b+
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8Gb: x4, x8, x16 DDR3L SDRAM Input Clock Frequency Change Input Clock Frequency Change When the DDR3 SDRAM is initialized, the clock must be stable during most normal states of operation. This means that after the clock frequency has been set to the stable state, the clock period is not allowed to deviate, except for what is allowed by the clock jitter and spread spectrum clocking (SSC) specifications.
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8Gb: x4, x8, x16 DDR3L SDRAM Input Clock Frequency Change Figure 42: Change Frequency During Precharge Power-Down Previous clock frequency T0 T1 T2 New clock frequency Ta0 Tb0 Tc1 Tc0 Td0 Td1 Te0 Te1 CK# CK tCH tCH b tCL tCKSRE tIS tCL b tCH b tCK b tCL b tCK b tCKSRX tCKE tIH CKE tIS tCPDED Command tCH b tCK b tCK tIH tCL b NOP NOP NOP NOP NOP Address MRS NOP Valid DLL RESET tAOFPD/tAOF tXP Valid tIH tIS ODT DQS, DQS# High-Z DQ High-Z DM tDLLK Enter prec
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8Gb: x4, x8, x16 DDR3L SDRAM Write Leveling Write Leveling For better signal integrity, DDR3 SDRAM memory modules have adopted fly-by topology for the commands, addresses, control signals, and clocks. Write leveling is a scheme for the memory controller to adjust or de-skew the DQS strobe (DQS, DQS#) to CK relationship at the DRAM with a simple feedback feature provided by the DRAM. Write leveling is generally used as part of the initialization process, if required.
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8Gb: x4, x8, x16 DDR3L SDRAM Write Leveling When write leveling is enabled, the rising edge of DQS samples CK, and the prime DQ outputs the sampled CK’s status. The prime DQ for a x4 or x8 configuration is DQ0 with all other DQ (DQ[7:1]) driving LOW. The prime DQ for a x16 configuration is DQ0 for the lower byte and DQ8 for the upper byte. It outputs the status of CK sampled by LDQS and UDQS. All other DQ (DQ[7:1], DQ[15:9]) continue to drive LOW.
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8Gb: x4, x8, x16 DDR3L SDRAM Write Leveling Write Leveling Procedure A memory controller initiates the DRAM write leveling mode by setting MR1[7] to 1, assuming the other programable features (MR0, MR1, MR2, and MR3) are first set and the DLL is fully reset and locked. The DQ balls enter the write leveling mode going from a High-Z state to an undefined driving state, so the DQ bus should not be driven. During write leveling mode, only the NOP or DES commands are allowed.
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8Gb: x4, x8, x16 DDR3L SDRAM Write Leveling Figure 44: Write Leveling Sequence T1 T2 tWLS tWLH CK# CK Command MRS1 NOP2 NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP tMOD ODT tWLDQSEN tDQSL3 tDQSH3 tDQSL3 tDQSH3 Differential DQS4 tWLMRD tWLO tWLO Prime DQ5 tWLO tWLOE Early remaining DQ tWLO Late remaining DQ Indicates break in time scale Notes: Undefined Driving Mode Don’t Care 1. MRS: Load MR1 to enter write leveling mode. 2. NOP: NOP or DES. 3.
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8Gb: x4, x8, x16 DDR3L SDRAM Write Leveling Write Leveling Mode Exit Procedure After the DRAM are leveled, they must exit from write leveling mode before the normal mode can be used. Figure 45 depicts a general procedure for exiting write leveling mode. After the last rising DQS (capturing a 1 at T0), the memory controller should stop driving the DQS signals after tWLO (MAX) delay plus enough delay to enable the memory controller to capture the applicable prime DQ state (at ~Tb0).
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8Gb: x4, x8, x16 DDR3L SDRAM Initialization Initialization The following sequence is required for power-up and initialization, as shown in Figure 46 (page 127): 1. Apply power. RESET# is recommended to be below 0.2 × V DDQ during power ramp to ensure the outputs remain disabled (High-Z) and ODT off (RTT is also High-Z). All other inputs, including ODT, may be undefined. During power-up, either of the following conditions may exist and must be met: 2. 3. 4. 5. 6. 7. 8. 9. 10. 11.
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8Gb: x4, x8, x16 DDR3L SDRAM Initialization Figure 46: Initialization Sequence T (MAX) = 200ms VDD VDDQ VTT See power-up conditions in the initialization sequence text, set up 1 VREF Power-up ramp tVTD Stable and valid clock T0 T1 tCK Tc0 Tb0 Ta0 Td0 CK# CK tCKSRX tIOZ tCL tCL = 20ns RESET# tIS T (MIN) = 10ns CKE Valid ODT Valid tIS Command NOP MRS MRS MRS MRS Address Code Code Code Code A10 Code Code Code Code BA0 = L BA1 = H BA2 = L BA0 = H BA1 = H BA2 = L BA0 = H B
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8Gb: x4, x8, x16 DDR3L SDRAM Voltage Initialization / Change Voltage Initialization / Change If the SDRAM is powered up and initialized for the 1.35V operating voltage range, voltage can be increased to the 1.5V operating range provided the following conditions are met (See Figure 47 (page 129)): • Just prior to increasing the 1.35V operating voltages, no further commands are issued, other than NOPs or COMMAND INHIBITs, and all banks are in the precharge state. • The 1.
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8Gb: x4, x8, x16 DDR3L SDRAM Voltage Initialization / Change VDD Voltage Switching After the DDR3L DRAM is powered up and initialized, the power supply can be altered between the DDR3L and DDR3 levels, provided the sequence in Figure 47 is maintained.
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8Gb: x4, x8, x16 DDR3L SDRAM Mode Registers Mode Registers Mode registers (MR0–MR3) are used to define various modes of programmable operations of the DDR3 SDRAM. A mode register is programmed via the mode register set (MRS) command during initialization, and it retains the stored information (except for MR0[8], which is self-clearing) until it is reprogrammed, RESET# goes LOW, the device loses power. Contents of a mode register can be altered by re-executing the MRS command.
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8Gb: x4, x8, x16 DDR3L SDRAM Mode Register 0 (MR0) Figure 49: MRS to nonMRS Command Timing (tMOD) T0 T1 T2 Ta0 Ta1 Ta2 MRS NOP NOP NOP NOP non MRS CK# CK Command tMOD Address Valid Valid Valid CKE Old setting New setting Updating setting Indicates break in time scale Notes: Don’t Care 1. Prior to issuing the MRS command, all banks must be idle (they must be precharged, tRP must be satisfied, and no data bursts can be in progress). 2.
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8Gb: x4, x8, x16 DDR3L SDRAM Mode Register 0 (MR0) ing location within the block. The programmed burst length applies to both READ and WRITE bursts.
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8Gb: x4, x8, x16 DDR3L SDRAM Mode Register 0 (MR0) Table 73: Burst Order Burst Length READ/ WRITE Starting Column Address (A[2, 1, 0]) Burst Type = Sequential (Decimal) Burst Type = Interleaved (Decimal) Notes 4 (chop) READ 000 0, 1, 2, 3, Z, Z, Z, Z 0, 1, 2, 3, Z, Z, Z, Z 1, 2 001 1, 2, 3, 0, Z, Z, Z, Z 1, 0, 3, 2, Z, Z, Z, Z 1, 2 010 2, 3, 0, 1, Z, Z, Z, Z 2, 3, 0, 1, Z, Z, Z, Z 1, 2 011 3, 0, 1, 2, Z, Z, Z, Z 3, 2, 1, 0, Z, Z, Z, Z 1, 2 100 4, 5, 6, 7, Z, Z, Z, Z 4, 5, 6, 7, Z,
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8Gb: x4, x8, x16 DDR3L SDRAM Mode Register 0 (MR0) quired to program the correct value of write recovery, which is calculated by dividing (ns) by tCK (ns) and rounding up a noninteger value to the next integer: WR (cycles) = roundup (tWR (ns)/tCK (ns)). tWR Precharge Power-Down (Precharge PD) The precharge power-down (precharge PD) bit applies only when precharge powerdown mode is being used.
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8Gb: x4, x8, x16 DDR3L SDRAM Mode Register 1 (MR1) Mode Register 1 (MR1) The mode register 1 (MR1) controls additional functions and features not available in the other mode registers: Q OFF (OUTPUT DISABLE), TDQS (for the x8 configuration only), DLL ENABLE/DLL DISABLE, RTT,nom value (ODT), WRITE LEVELING, POSTED CAS ADDITIVE latency, and OUTPUT DRIVE STRENGTH. These functions are controlled via the bits shown in Figure 52 (page 135).
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8Gb: x4, x8, x16 DDR3L SDRAM Mode Register 1 (MR1) upon exit of SELF REFRESH operation. If the DLL is disabled prior to entering self refresh mode, the DLL remains disabled even upon exit of SELF REFRESH operation until it is re-enabled and reset. The DRAM is not tested to check—nor does Alliance Memory warrant compliance with —normal mode timings or functionality when the DLL is disabled.
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8Gb: x4, x8, x16 DDR3L SDRAM Mode Register 1 (MR1) vided, and the TDQS# ball is not used. The TDQS function is available in the x8 DDR3 SDRAM configuration only and must be disabled via the mode register for the x4 and x16 configurations. On-Die Termination ODT resistance RTT,nom is defined by MR1[9, 6, 2] (see Figure 52 (page 135)). The R TT termination value applies to the DQ, DM, DQS, DQS#, and TDQS, TDQS# balls.
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8Gb: x4, x8, x16 DDR3L SDRAM Mode Register 2 (MR2) the AL and CAS latency (CL), RL = AL + CL. WRITE latency (WL) is the sum of CAS WRITE latency and AL, WL = AL + CWL (see Mode Register 2 (MR2) (page 138)). Examples of READ and WRITE latencies are shown in Figure 53 (page 138) and Figure 55 (page 139).
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8Gb: x4, x8, x16 DDR3L SDRAM Mode Register 2 (MR2) Figure 54: Mode Register 2 (MR2) Definition BA2 BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address bus 16 15 14 13 12 11 10 9 8 7 6 0 01 01 01 RTT(WR) 01 SRT ASR Mode register 2 (MR2) 5 01 1 M15 M14 Mode Register 3 M5 M4 M3 2 1 0 01 01 01 CAS Write Latency (CWL) 5 CK (tCK ≥2.
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8Gb: x4, x8, x16 DDR3L SDRAM Mode Register 2 (MR2) sure the DRAM never exceeds a T C of 85°C while in self refresh unless the user enables the SRT feature listed below when the T C is between 85°C and 95°C. Enabling ASR assumes the DRAM self refresh rate is changed automatically from 1x to 2x when the case temperature exceeds 85°C. This enables the user to operate the DRAM beyond the standard 85°C limit up to the optional extended temperature range of 95°C while in self refresh mode.
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8Gb: x4, x8, x16 DDR3L SDRAM Mode Register 3 (MR3) back to ODT (RTT,nom) at the completion of the WRITE burst. If R TT,nom is disabled, the RTT,nom value will be High-Z. Special timing parameters must be adhered to when dynamic ODT (RTT(WR)) is enabled: ODTLcnw, ODTLcnw4, ODTLcnw8, ODTH4, ODTH8, and tADC. Dynamic ODT is only applicable during WRITE cycles. If ODT (R TT,nom) is disabled, dynamic ODT (RTT(WR)) is still permitted. RTT,nom and RTT(WR) can be used independent of one other.
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8Gb: x4, x8, x16 DDR3L SDRAM Mode Register 3 (MR3) and tRP is met). When the MPR is enabled, any subsequent READ or RDAP commands are redirected to the multipurpose register. The resulting operation when either a READ or a RDAP command is issued, is defined by MR3[1:0] when the MPR is enabled (see Table 75 (page 143)). When the MPR is enabled, only READ or RDAP commands are allowed until a subsequent MRS command is issued with the MPR disabled (MR3[2] = 0).
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8Gb: x4, x8, x16 DDR3L SDRAM Mode Register 3 (MR3) MPR addressing for a valid MPR read is as follows: • A[1:0] must be set to 00 as the burst order is fixed per nibble • A2 selects the burst order: – BL8, A2 is set to 0, and the burst order is fixed to 0, 1, 2, 3, 4, 5, 6, 7 • For burst chop 4 cases, the burst order is switched on the nibble base along with the following: • • • • • • • – A2 = 0; burst order = 0, 1, 2, 3 – A2 = 1; burst order = 4, 5, 6, 7 Burst order bit 0 (the first bit) is assigned to LS
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8Gb: x4, x8, x16 DDR3L SDRAM Mode Register 3 (MR3) Table 75: MPR Readouts and Burst Order Bit Mapping (Continued) MR3[2] MR3[1:0] Function Burst Length Read A[2:0] Burst Order and Data Pattern 1 11 RFU N/A N/A N/A N/A N/A N/A N/A N/A N/A Note: 1. Burst order bit 0 is assigned to LSB, and burst order bit 7 is assigned to MSB of the selected MPR agent. Rev 2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc.
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Rev 2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc. reserves the right to change products or specification without notice 145 DQ DQS, DQS# A[15:13] tMOD Notes: 0 0 A12/BC# 0 A10/AP 0 00 A[9:3] A11 1 A2 1 0 A[1:0] tRP MRS Ta0 3 PREA T0 Bank address Command CK# CK NOP Tc4 NOP Tc5 NOP Tc6 tMPRR MRS Tc7 1. READ with BL8 either by MRS or OTF. 2. Memory controller must drive 0 on A[2:0].
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Rev 2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc. reserves the right to change products or specification without notice 146 DQ tMOD Notes: 0 A[15:13] DQS, DQS# 0 A12/BC# 0 A10/AP 0 00 A[9:3] A11 1 A2 1 0 MRS A[1:0] tRP Ta 3 PREA T0 Bank address Command CK# CK RL NOP Tc6 NOP Tc7 NOP Tc8 tMPRR Indicates break in time scale NOP Tc9 0 00 0 Valid 3 MRS Tc10 RL Valid 1. READ with BL8 either by MRS or OTF. 2.
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Rev 2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc. reserves the right to change products or specification without notice 147 DQ tMOD Notes: 0 A[15:13] DQS, DQS# 0 A12/BC# 0 A10/AP 0 00 A[9:3] A11 1 A2 1 0 A[1:0] tRF MRS Ta 3 PREA T0 Bank address Command CK# CK 14 03 1. 2. 3. 4. NOP Tc1 NOP Tc2 RL NOP Tc3 READ with BC4 either by MRS or OTF. Memory controller must drive 0 on A[1:0]. A2 = 0 selects lower 4 nibble bits 0 . . . 3.
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Rev 2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc. reserves the right to change products or specification without notice 148 DQ tMOD Notes: 0 A[15:13] DQS, DQS# 0 A12/BC# 0 A10/AP 0 00 A[9:3] A11 1 A2 1 0 A[1:0] tRF MRS Ta 3 PREA T0 Bank address Command CK# CK 04 13 1. 2. 3. 4. NOP Tc1 NOP Tc2 RL NOP Tc3 READ with BC4 either by MRS or OTF. Memory controller must drive 0 on A[1:0]. A2 = 1 selects upper 4 nibble bits 4 . . . 7.
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8Gb: x4, x8, x16 DDR3L SDRAM MODE REGISTER SET (MRS) Command MPR Read Predefined Pattern The predetermined read calibration pattern is a fixed pattern of 0, 1, 0, 1, 0, 1, 0, 1. The following is an example of using the read out predetermined read calibration pattern. The example is to perform multiple reads from the multipurpose register to do system level read timing calibration based on the predetermined and standardized pattern.
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8Gb: x4, x8, x16 DDR3L SDRAM ZQ CALIBRATION Operation ZQ CALIBRATION Operation The ZQ CALIBRATION command is used to calibrate the DRAM output drivers (RON) and ODT values (RTT) over process, voltage, and temperature, provided a dedicated 240Ω (±1%) external resistor is connected from the DRAM’s ZQ ball to V SSQ. DDR3 SDRAM require a longer time to calibrate RON and ODT at power-up initialization and self refresh exit, and a relatively shorter time to perform periodic calibrations.
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8Gb: x4, x8, x16 DDR3L SDRAM ACTIVATE Operation ACTIVATE Operation Before any READ or WRITE commands can be issued to a bank within the DRAM, a row in that bank must be opened (activated). This is accomplished via the ACTIVATE command, which selects both the bank and the row to be activated. After a row is opened with an ACTIVATE command, a READ or WRITE command may be issued to that row, subject to the tRCD specification.
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8Gb: x4, x8, x16 DDR3L SDRAM ACTIVATE Operation Figure 64: Example: tFAW CK# T0 T1 T4 T5 T8 T9 T10 T11 T19 T20 ACT NOP ACT NOP ACT NOP ACT NOP NOP ACT CK Command Address BA[2:0] Row Row Row Row Row Bank a Bank b Bank c Bank d Bank ey tRRD tFAW Indicates break in time scale Rev 2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc. reserves the right to change products or specification without notice 152 Don’t Care Alliance Memory Inc.
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8Gb: x4, x8, x16 DDR3L SDRAM READ Operation READ Operation READ bursts are initiated with a READ command. The starting column and bank addresses are provided with the READ command and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is automatically precharged at the completion of the burst. If auto precharge is disabled, the row will be left open after the completion of the burst.
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8Gb: x4, x8, x16 DDR3L SDRAM READ Operation Figure 68 (page 156). DDR3 SDRAM does not allow interrupting or truncating any READ burst. Data from any READ burst must be completed before a subsequent WRITE burst is allowed. An example of a READ burst followed by a WRITE burst for BL8 is shown in Figure 69 (page 156) (BC4 is shown in Figure 70 (page 157)). To ensure the READ data is completed before the WRITE data is on the bus, the minimum READ-to-WRITE timing is RL + tCCD - WL + 2 tCK.
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8Gb: x4, x8, x16 DDR3L SDRAM READ Operation DQS to DQ output timing is shown in Figure 75 (page 160). The DQ transitions between valid data outputs must be within tDQSQ of the crossing point of DQS, DQS#. DQS must also maintain a minimum HIGH and LOW time of tQSH and tQSL. Prior to the READ preamble, the DQ balls will either be floating or terminated, depending on the status of the ODT signal. Figure 76 (page 161) shows the strobe-to-clock timing during a READ.
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All DQ collectively DQ3 (first data no longer valid) DQ3 (last data valid) Notes: Bank, Col n Address2 DQS, DQS# READ T0 Command1 CK CK# Rev 2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc.
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8Gb: x4, x8, x16 DDR3L SDRAM READ Operation tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level that specifies when the device output is no longer driving tHZDQS and tHZDQ, or begins driving tLZDQS, tLZDQ. Figure 77 (page 162) shows a method of calculating the point when the device is no longer driving tHZDQS and tHZDQ, or begins driving tLZDQS, tLZDQ, by measuring the signal at two different voltages.
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8Gb: x4, x8, x16 DDR3L SDRAM READ Operation Figure 77: Method for Calculating tLZ and tHZ VOH - xmV VTT + 2xmV VOH - 2xmV VTT + xmV tLZDQS, tLZDQ tHZDQS, tHZDQ T2 T1 tHZDQS, tHZDQ VOL + 2xmV VTT - xmV VOL + xmV VTT - 2xmV T1 T2 tLZDQS, tLZDQ end point = 2 × T1 - T2 begin point = 2 × T1 - T2 1. Within a burst, the rising strobe edge is not necessarily fixed at tDQSCK (MIN) or tDQSCK (MAX). Instead, the rising strobe edge can vary between tDQSCK (MIN) and tDQSCK (MAX). 2.
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8Gb: x4, x8, x16 DDR3L SDRAM READ Operation Figure 79: tRPST Timing CK VTT CK# tA DQS Single-ended signal, provided as background information t VTT B tC tD DQS# VTT Single-ended signal, provided as background information tRPST DQS - DQS# Resulting differential signal relevant for tRPST specification Rev 2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc.
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8Gb: x4, x8, x16 DDR3L SDRAM WRITE Operation WRITE Operation WRITE bursts are initiated with a WRITE command. The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge is selected, the row being accessed is precharged at the end of the WRITE burst. If auto precharge is not selected, the row will remain open for subsequent accesses.
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8Gb: x4, x8, x16 DDR3L SDRAM WRITE Operation Figure 80: tWPRE Timing CK VTT CK# T1 begins tWPRE DQS - DQS# 0V tWPRE T2 Resulting differential signal relevant for tWPRE specification tWPRE ends Figure 81: tWPST Timing CK VTT CK# tWPST DQS - DQS# Resulting differential signal relevant for tWPST specification 0V T1 begins tWPST T2 ends tWPST Rev 2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc.
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8Gb: x4, x8, x16 DDR3L SDRAM WRITE Operation Figure 82: WRITE Burst T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 WRITE NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP CK# CK Command1 WL = AL + CWL Address2 Bank, Col n tDQSS tWPRE (MIN) tDQSS tDSH tDSH tDSH tDSH tWPST DQS, DQS# tDQSH tDQSL tDQSH DI n DQ3 tDQSS DI n+1 tWPRE (NOM) tDQSL tDQSH DI n+2 tDQSL DI n+3 tDSH tDQSH DI n+4 tDQSL DI n+5 tDSH tDQSH DI n+6 tDQSL DI n+7 tDSH tDSH tWPST tDQSH tDQSL DQS, DQS# tDQSH t
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Valid Address2 Rev 2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc. reserves the right to change products or specification without notice NOP T1 Notes: tCCD NOP T2 Valid WRITE T4 tWPRE DI n NOP T5 DI n+1 DI n+2 NOP T6 167 Valid Address2 DQ3 DQS, DQS# WRITE T0 Command1 CK CK# NOP T1 Notes: tCCD 1. 2. 3. 4. 5.
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Valid Address3 DQ4 DQS, DQS# WRITE T0 Command1 CK CK# Notes: NOP T1 Rev 2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc. reserves the right to change products or specification without notice WL = 5 NOP T3 NOP T4 tWPRE DI n NOP T5 DI n+1 DI n+2 NOP T6 DI n+3 tWPST NOP T7 Indicates break in time scale NOP T8 Transitioning Data tWTR2 NOP T9 Don’t Care Valid READ Ta0 1.
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Valid Address3 DQ4 DQS, DQS# WRITE T0 Command1 CK CK# Notes: NOP T1 WL = 5 NOP T3 NOP T4 tWPRE DI n NOP T5 DI n+1 DI n+2 NOP T6 NOP = 4 clocks DI n+3 tWPST tBL T7 NOP T8 NOP T9 Indicates break in time scale tWTR2 NOP T10 Transitioning Data NOP T11 RL = 5 Don’t Care Valid READ Tn 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. tWTR controls the WRITE-to-READ delay to the same device and starts after tBL. 3.
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8Gb: x4, x8, x16 DDR3L SDRAM WRITE Operation Figure 89: WRITE (BL8) to PRECHARGE T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 Ta0 Ta1 Command WRITE NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP PRE Address Valid CK# CK Valid tWR WL = AL + CWL DQS, DQS# DI n DQ BL8 DI n+1 DI n+2 DI n+3 DI n+4 DI n+5 DI n+6 DI n+7 Indicates break in time scale Notes: Transitioning Data Don’t Care 1. DI n = data-in from column n. 2.
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8Gb: x4, x8, x16 DDR3L SDRAM WRITE Operation Figure 91: WRITE (BC4 OTF) to PRECHARGE T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 WRITE NOP NOP NOP NOP NOP NOP NOP NOP NOP Tn CK# CK Command1 PRE tWR2 Address3 Bank, Col n Valid tWPRE tWPST DQS, DQS# DI n DQ4 DI n+1 DI n+2 DI n+3 WL = 5 Indicates break in time scale Notes: Transitioning Data Don’t Care 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2.
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8Gb: x4, x8, x16 DDR3L SDRAM WRITE Operation Figure 92: Data Input Timing DQS, DQS# tWPRE DQ tDQSH tWPST tDQSL DI b DM tDS tDH tDS tDH Transitioning Data Rev.2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc. reserves the right to change products or specification without notice 173 Don’t Care Alliance Memory Inc.
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8Gb: x4, x8, x16 DDR3L SDRAM PRECHARGE Operation PRECHARGE Operation Input A10 determines whether one bank or all banks are to be precharged and, in the case where only one bank is to be precharged, inputs BA[2:0] select the bank. When all banks are to be precharged, inputs BA[2:0] are treated as “Don’t Care.” After a bank is precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued.
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8Gb: x4, x8, x16 DDR3L SDRAM SELF REFRESH Operation Figure 93: Self Refresh Entry/Exit Timing T0 T1 T2 Ta0 Tb0 Tc0 Tc1 Td0 Te0 Tf0 Valid Valid CK# CK tCKSRX1 tCKSRE1 tIS tIH tCPDED tIS CKE tCKESR (MIN)1 tIS ODT2 Valid ODTL RESET#2 Command NOP SRE (REF)3 NOP4 SRX (NOP) NOP5 Address tRP8 Valid 6 Valid 7 Valid Valid tXS6, 9 tXSDLL7, 9 Enter self refresh mode (synchronous) Exit self refresh mode (asynchronous) Indicates break in time scale Notes: Don’t Care 1.
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8Gb: x4, x8, x16 DDR3L SDRAM Extended Temperature Usage Extended Temperature Usage Alliance Memory’s DDR3 SDRAM support the optional extended case temperature (TC) range of 0°C to 95°C. Thus, the SRT and ASR options must be used at a minimum. The extended temperature range DRAM must be refreshed externally at 2x (double refresh) anytime the case temperature is above 85°C (and does not exceed 95°C). The external refresh requirement is accomplished by reducing the refresh period from 64ms to 32ms.
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8Gb: x4, x8, x16 DDR3L SDRAM Power-Down Mode Power-Down Mode Power-down is synchronously entered when CKE is registered LOW coincident with a NOP or DES command. CKE is not allowed to go LOW while an MRS, MPR, ZQCAL, READ, or WRITE operation is in progress. CKE is allowed to go LOW while any of the other legal operations (such as ROW ACTIVATION, PRECHARGE, auto precharge, or REFRESH) are in progress. However, the power-down IDD specifications are not applicable until such operations have completed.
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8Gb: x4, x8, x16 DDR3L SDRAM Power-Down Mode exit mode precharge power-down. A summary of the two power-down modes is listed in Table 79 (page 178). While in either power-down state, CKE is held LOW, RESET# is held HIGH, and a stable clock signal must be maintained. ODT must be in a valid state but all other input signals are “Don’t Care.” If RESET# goes LOW during power-down, the DRAM will switch out of power-down mode and go into the reset state.
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8Gb: x4, x8, x16 DDR3L SDRAM Power-Down Mode Figure 94: Active Power-Down Entry and Exit T0 T1 T2 Ta0 Ta1 Ta2 Ta3 Ta4 NOP NOP NOP Valid CK# CK Command tCK tCH tCL NOP Valid NOP tPD tIS CKE Address tIH tIH tCKE tIS (MIN) Valid Valid tXP tCPDED Enter power-down mode Exit power-down mode Indicates break in time scale Don’t Care Figure 95: Precharge Power-Down (Fast-Exit Mode) Entry and Exit T0 T1 T2 T3 T4 T5 NOP NOP Ta0 Ta1 NOP Valid CK# CK t t CK t CH Comman
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8Gb: x4, x8, x16 DDR3L SDRAM Power-Down Mode Figure 96: Precharge Power-Down (Slow-Exit Mode) Entry and Exit T0 T1 T2 T3 T4 Ta NOP NOP Ta1 Tb CK# CK tCK Command tCH tCL NOP PRE NOP tCKE tCPDED Valid 1 Valid 2 (MIN) tXP tIH tIS CKE tXPDLL tIS tPD Enter power-down mode Exit power-down mode Indicates break in time scale Notes: Don’t Care 1. Any valid command not requiring a locked DLL. 2. Any valid command requiring a locked DLL.
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8Gb: x4, x8, x16 DDR3L SDRAM Power-Down Mode Figure 98: Power-Down Entry After WRITE CK# T0 T1 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Tb0 WRITE NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP Tb1 Tb2 Tb3 Tb4 CK Command NOP tIS NOP tCPDED CKE Address Valid tWR WL = AL + CWL tPD DQS, DQS# DQ BL8 DI n DI DI n+1 n+2 DI n+3 DQ BC4 DI n DI n+1 DI n+3 DI n+2 DI n+4 DI DI n+5 n+6 DI n+7 tWRPDEN Power-down or self refresh entry1 Indicates break in time scale Note: Transitioning
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8Gb: x4, x8, x16 DDR3L SDRAM Power-Down Mode Figure 100: REFRESH to Power-Down Entry T0 T1 T2 T3 Ta0 NOP NOP Ta1 Ta2 Tb0 CK# CK tCK Command tCH tCL REFRESH NOP tCPDED NOP tCKE Valid (MIN) tPD tIS CKE tREFPDEN tXP tRFC (MIN) (MIN)1 Indicates break in time scale Note: Don’t Care 1. After CKE goes HIGH during tRFC, CKE must remain HIGH until tRFC is satisfied.
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8Gb: x4, x8, x16 DDR3L SDRAM Power-Down Mode Figure 102: PRECHARGE to Power-Down Entry T0 T1 T2 T3 NOP NOP T4 T5 T6 T7 CK# CK tCK Command tCH tCL PRE All/single bank Address tCPDED tIS tPD CKE tPREPDEN Don’t Care Figure 103: MRS Command to Power-Down Entry T0 T1 T2 Ta0 Ta1 Ta2 Ta3 Ta4 CK# CK tCK Command MRS Address Valid tCH NOP tCPDED tCL NOP NOP NOP tMRSPDEN NOP tPD tIS CKE Indicates break in time scale Rev.2.0 June 2016 © 2015 Alliance Memory, Inc.
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8Gb: x4, x8, x16 DDR3L SDRAM Power-Down Mode Figure 104: Power-Down Exit to Refresh to Power-Down Entry T0 T1 T2 T3 T4 Ta0 NOP REFRESH Ta1 Tb0 CK# CK Command tCK tCH NOP tCL NOP NOP tCPDED NOP NOP tXP1 tIH tIS CKE tIS tPD tXPDLL2 Enter power-down mode Enter power-down mode Exit power-down mode Indicates break in time scale Notes: Don’t Care 1. tXP must be satisfied before issuing the command. 2.
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8Gb: x4, x8, x16 DDR3L SDRAM RESET Operation RESET Operation The RESET signal (RESET#) is an asynchronous reset signal that triggers any time it drops LOW, and there are no restrictions about when it can go LOW. After RESET# goes LOW, it must remain LOW for 100ns. During this time, the outputs are disabled, ODT (RTT) turns off (High-Z), and the DRAM resets itself. CKE should be driven LOW prior to RESET# being driven HIGH.
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8Gb: x4, x8, x16 DDR3L SDRAM RESET Operation Figure 105: RESET Sequence System RESET (warm boot) Stable and valid clock T0 T1 tCK Tc0 Tb0 Ta0 Td0 CK# CK tCL tCL t CKSRX1 T = 100ns (MIN) RESET# tIOZ = 20ns T = 10ns (MIN) tIS Valid CKE tIS tIS Static LOW in case RTT_Nom is enabled at time Ta0, otherwise static HIGH or LOW ODT Valid tIS MRS MRS MRS MRS Address Code Code Code Code A10 Code Code Code Code BA0 = L BA1 = H BA2 = L BA0 = H BA1 = H BA2 = L BA0 = H BA1 = L BA2 =
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8Gb: x4, x8, x16 DDR3L SDRAM On-Die Termination (ODT) On-Die Termination (ODT) On-die termination (ODT) is a feature that enables the DRAM to enable/disable and turn on/off termination resistance for each DQ, DQS, DQS#, and DM for the x4 and x8 configurations (and TDQS, TDQS# for the x8 configuration, when enabled). ODT is applied to each DQ, UDQS, UDQS#, LDQS, LDQS#, UDM, and LDM signal for the x16 configuration.
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8Gb: x4, x8, x16 DDR3L SDRAM On-Die Termination (ODT) Table 80: Truth Table – ODT (Nominal) Note 1 applies to the entire table MR1[9, 6, 2] ODT Pin DRAM Termination State DRAM State Notes 000 0 RTT,nom disabled, ODT off Any valid 2 000 1 RTT,nom disabled, ODT on Any valid except self refresh, read 3 000–101 0 RTT,nom enabled, ODT off Any valid 2 000–101 1 RTT,nom enabled, ODT on Any valid except self refresh, read 3 110 and 111 X RTT,nom reserved, ODT on or off Illegal Notes: 1
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8Gb: x4, x8, x16 DDR3L SDRAM Dynamic ODT Dynamic ODT In certain application cases, and to further enhance signal integrity on the data bus, it is desirable that the termination strength of the DDR3 SDRAM can be changed without issuing an MRS command, essentially changing the ODT termination on the fly.
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8Gb: x4, x8, x16 DDR3L SDRAM Dynamic ODT • During DRAM operation without READ or WRITE commands, the termination is controlled. – Nominal termination strength RTT,nom is used. – Termination on/off timing is controlled via the ODT ball and latencies ODTLon and ODTLoff. • When a WRITE command (WR, WRAP, WRS4, WRS8, WRAPS4, WRAPS8) is registered, and if dynamic ODT is enabled, the ODT termination is controlled.
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8Gb: x4, x8, x16 DDR3L SDRAM Dynamic ODT Table 85: Mode Registers for RTT(WR) MR2 (RTT(WR)) M10 M9 RTT(WR) (RZQ) RTT(WR) (Ohm) 0 0 Dynamic ODT off: WRITE does not affect RTT,nom 0 1 RZQ/4 1 0 RZQ/2 120 1 1 Reserved Reserved 60 Table 86: Timing Diagrams for Dynamic ODT Figure and Page Title Figure 107 (page 192) Dynamic ODT: ODT Asserted Before and After the WRITE, BC4 Figure 108 (page 192) Dynamic ODT: Without WRITE Command Figure 109 (page 193) Dynamic ODT: ODT Pin Asserted Togeth
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8Gb: x4, x8, x16 DDR3L SDRAM Dynamic ODT Figure 110: Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4 T0 T1 T2 NOP WRS4 NOP T3 T4 T5 T6 T7 T8 T9 T10 T11 NOP NOP NOP NOP NOP NOP NOP NOP NOP CK# CK Command ODTLcnw Address Valid ODTH4 ODTLoff ODT ODTLon tADC tADC (MAX) RTT(WR) RTT tAON tADC (MIN) tAOF (MIN) RTT,nom tAOF (MAX) (MIN) (MAX) ODTLcwn4 DQS, DQS# DI n DQ DI n+1 DI n+2 DI n+3 WL Transitioning Notes: Don’t Care 1. Via MRS or OTF.
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8Gb: x4, x8, x16 DDR3L SDRAM Synchronous ODT Mode Synchronous ODT Mode Synchronous ODT mode is selected whenever the DLL is turned on and locked and when either RTT,nom or RTT(WR) is enabled.
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RTT ODT Command CKE CK# CK NOP T0 NOP T1 Notes: NOP T2 NOP T4 NOP T5 NOP T6 ODTH4 (MIN) NOP T8 (MAX) (MIN) tAON tAON ODTH4 NOP T9 RTT,nom tAOF ODTLon = WL - 2 ODTLoff = WL - 2 WRS4 T7 tAOF (MIN) NOP T10 (MAX) tAON NOP T11 (MIN) tAON (MAX) NOP T12 NOP T14 RTT,nom ODTLoff = WL - 2 NOP T13 NOP T16 Transitioning NOP T15 Don’t Care (MAX) (MIN) tAOF tAOF NOP T17 WL = 7. RTT,nom is enabled. RTT(WR) is disabled.
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8Gb: x4, x8, x16 DDR3L SDRAM Synchronous ODT Mode ODT Off During READs Because the device cannot terminate and drive at the same time, RTT must be disabled at least one-half clock cycle before the READ preamble by driving the ODT ball LOW (if either RTT,nom or RTT(WR) is enabled). RTT may not be enabled until the end of the postamble, as shown in the following example. Note: ODT may be disabled earlier and enabled later than shown in Figure 114 (page 199). Rev.2.0 June 2016 © 2015 Alliance Memory, Inc.
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Valid Address DQ DQS, DQS# RTT ODT READ T0 Command CK# CK NOP T1 Note: NOP T2 NOP T5 NOP T6 RL = AL + CL RTT,nom ODTLoff = CWL + AL - 2 NOP T4 NOP T7 NOP T8 NOP T9 (MAX) (MIN) tAOF tAOF NOP T11 DI b DI b+1 DI b+2 NOP T12 ODTLon = CWL + AL - 2 NOP T10 DI b+3 DI b+4 NOP T13 DI b+5 DI b+6 NOP T14 tAON NOP T17 Don’t Care (MAX) RTT,nom NOP T16 Transitioning DI b+7 NOP T15 1. ODT must be disabled externally during READs by driving ODT LOW.
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8Gb: x4, x8, x16 DDR3L SDRAM Asynchronous ODT Mode Asynchronous ODT Mode Asynchronous ODT mode is available when the DRAM runs in DLL on mode and when either RTT,nom or RTT(WR) is enabled; however, the DLL is temporarily turned off in precharged power-down standby (via MR0[12]). Additionally, ODT operates asynchronously when the DLL is synchronizing after being reset. See Power-Down Mode (page 177) for definition and guidance over power-down details.
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T0 T1 Note: T2 tIS T4 (MIN) tAONPD tAONPD T5 1. AL is ignored. tIH T3 (MAX) T6 T7 T8 T9 Description Asynchronous RTT turn-on delay (power-down with DLL off) Asynchronous RTT turn-off delay (power-down with DLL off) Symbol tAONPD tAOFPD Table 88: Asynchronous ODT Timing Parameters for All Speed Bins RTT ODT CKE CK# CK Figure 115: Asynchronous ODT Timing with Fast ODT Transition RTT,nom T10 tIH T11 tIS T12 Rev.2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved.
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8Gb: x4, x8, x16 DDR3L SDRAM Asynchronous ODT Mode Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry) There is a transition period around power-down entry (PDE) where the DRAM’s ODT may exhibit either synchronous or asynchronous behavior. This transition period occurs if the DLL is selected to be off when in precharge power-down mode by the setting MR0[12] = 0. Power-down entry begins tANPD prior to CKE first being registered LOW, and ends when CKE is first registered LOW.
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8Gb: x4, x8, x16 DDR3L SDRAM Asynchronous to Synchronous ODT Mode Transition (PowerDown Exit) Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit) The DRAM’s ODT can exhibit either asynchronous or synchronous behavior during power-down exit (PDX). This transition period occurs if the DLL is selected to be off when in precharge power-down mode by setting MR0[12] to 0. Power-down exit begins tANPD prior to CKE first being registered HIGH, and ends tXPDLL after CKE is first registered HIGH.
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8Gb: x4, x8, x16 DDR3L SDRAM Asynchronous to Synchronous ODT Mode Transition (PowerDown Exit) Asynchronous to Synchronous ODT Mode Transition (Short CKE Pulse) If the time in the precharge power-down or idle states is very short (short CKE LOW pulse), the power-down entry and power-down exit transition periods overlap.
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207 Command CK# CK EKC Rev.2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc. reserves the right to change products or specification without notice REF T0 Note: NOP T1 tANPD NOP T3 NOP T5 NOP T7 (MIN) tANPD tRFC T8 NOP NOP T9 PDX transition period PDE transition period NOP T6 Short CKE low transition period (R TT change asynchronous or synchronous) NOP T4 1. AL = 0, WL = 5, tANPD = 4.
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8Gb: x4, x8, x16 DDR3L SDRAM Asynchronous to Synchronous ODT Mode Transition (PowerDown Exit) Rev.2.0 June 2016 © 2015 Alliance Memory, Inc. All rights reserved. Alliance Memory Inc. reserves the right to change products or specification without notice 208 Alliance Memory Inc.