Datasheet

ManualsBrandsAlliance Memory ManualsMemory ICsSRAM 2MB 55ns TSOP-II

FEATURES

Fast access time : 55ns

Low power consumption:

Operating current : 20/18mA (TYP.)

Standby current : 2µA (TYP.)

Single 2.7V ~ 5.5V power supply

All inputs and outputs TTL compatible

Fully static operation

Tri-state output

Data byte control : LB# (DQ0 ~ DQ7)

UB# (DQ8 ~ DQ15)

Data retention voltage : 2.0V (MIN.)

Lead free and green package available

Package : 44-pin 400 mil TSOP-II

48-ball 6mm x 8mm TFBGA

GENERAL DESCRIPTION

The AS6C2016 is a 2,097,152-bit low power

CMOS static random access memory organized as

131,0

72 words by 16 bits. It is fabricated using very

high

performance, high reliability CMOS technology.

Its standby current is stable within the range of

operating

temperature.

The

AS6C2016 is well designed for low power

appl

ication, and particularly well suited for battery

back-up

nonvolatile memory application.

The AS6C2016 operates from a single power

supply of 2.7V ~ 5.5V and all inputs and outputs are

fully

TTL compatible

PRODUCT FAMILY

Power Dissipation Product

Family

Operating

Temperature

Vcc

Range Speed

Standby(I

SB1,TYP.) Operating(Icc,TYP.)

AS6C2016 (I)

-40

~ 85℃

2.7

~ 5.5V 55ns 2µA 20/18mA

512K X 8 BIT LOW POWER CMOS SRAM

January 2007

128K X 16 BIT LOW POWER CMOS SRAM

FEBRUARY 2008

AS6C2016

FEBRUARY/2008, V 1.c

Alliance Memory Inc.

Page 1 of 13

Summary of content (13 pages)

PAGE 1
FEBRUARY 2008 January 2007 AS6C2016 512K X 8CMOS BIT LOW 128K X 16 BIT LOW POWER SRAMPOWER CMOS SRAM FEATURES GENERAL DESCRIPTION Fast access time : 55ns Low power consumption: Operating current : 20/18mA (TYP.) Standby current : 2µA (TYP.) Single 2.7V ~ 5.5V power supply All inputs and outputs TTL compatible Fully static operation Tri-state output Data byte control : LB# (DQ0 ~ DQ7) UB# (DQ8 ~ DQ15) Data retention voltage : 2.0V (MIN.
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FEBRUARY 2008 January 2007 AS6C2016 512K X 8CMOS BIT LOW 128K X 16 BIT LOW POWER SRAMPOWER CMOS SRAM FUNCTIONAL BLOCK DIAGRAM Vcc Vss A0-A16 DQ0-DQ7 Lower Byte DQ8-DQ15 Upper Byte CE# WE# OE# LB# UB# PIN DESCRIPTION SYMBOL DESCRIPTION A0 - A16 Address Inputs DQ0 – DQ15 Data Inputs/Outputs DECODER I/O DATA CIRCUIT 128Kx16 MEMORY ARRAY CE# Chip Enable Input WE# Write Enable Input OE# Output Enable Input LB# Lower Byte Control UB# Upper Byte Control VCC Power Supply VSS Ground COLUM
PAGE 3
FEBRUARY 2008 January 2007 AS6C2016 512K X 8CMOS BIT LOW 128K X 16 BIT LOW POWER SRAMPOWER CMOS SRAM PIN CONFIGURATION A4 1 44 A5 A3 2 43 A6 A2 3 42 A7 A1 4 41 OE# 5 40 UB# 6 39 LB# DQ0 7 38 DQ15 DQ1 8 37 DQ14 DQ2 9 36 DQ13 DQ3 10 35 DQ12 Vcc 11 34 Vss Vss 12 33 Vcc DQ4 13 32 DQ11 DQ5 14 31 DQ10 DQ6 15 30 AS6C2016 A0 CE# A LB# OE# A0 B DQ8 UB# A3 DQ9 C DQ9 DQ10 D Vss A2 NC A4 CE# DQ0 A5 A6 DQ1 DQ2 DQ11 NC A7 DQ3 Vcc E Vcc
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FEBRUARY 2008 January 2007 AS6C2016 512K X 8CMOS BIT LOW 128K X 16 BIT LOW POWER SRAMPOWER CMOS SRAM TRUTH TABLE MODE Standby Output Disable Read Write Note: CE# OE# H X L L L L L L L L X X H H L L L X X X WE# LB# X X H H H H H L L L UB# X H L X L H L L H L X H X L H L L H L L I/O OPERATION DQ0-DQ7 DQ8-DQ15 High – Z High – Z High – Z High – Z High – Z High – Z High – Z High – Z DOUT High – Z High – Z DOUT DOUT DOUT High – Z DIN High – Z DIN DIN DIN SUPPLY CURRENT ISB1 ICC,ICC1 ICC,ICC1 ICC,ICC1
PAGE 5
FEBRUARY 2008 January 2007 AS6C2016 512K X 8CMOS BIT LOW 128K X 16 BIT LOW POWER SRAMPOWER CMOS SRAM AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0.2V to VCC - 0.2V 3ns 1.
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FEBRUARY 2008 January 2007 AS6C2016 512K X 8CMOS BIT LOW 128K X 16 BIT LOW POWER SRAMPOWER CMOS SRAM TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) tRC Address tAA Dout tOH Previous Data Valid Data Valid READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5) tRC Address tAA CE# tACE LB#,UB# tBA OE# tOE tOH tOHZ tBHZ tCHZ tOLZ tBLZ tCLZ Dout High-Z Data Valid High-Z Notes : 1.WE#is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low, LB# or UB# = low. 3.
PAGE 7
FEBRUARY 2008 January 2007 AS6C2016 512K X 8CMOS BIT LOW 128K X 16 BIT LOW POWER SRAMPOWER CMOS SRAM WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6) tWC Address tAW CE# tCW tBW LB#,UB# tAS tWP tWR WE# tWHZ Dout T OW High-Z (4) (4) tDW tDH Data Valid Din WRITE CYCLE 2 (CE# Controlled) (1,2,5,6) tWC Address tAW CE# tAS tWR tCW tBW LB#,UB# tWP WE# tWHZ Dout (4) High-Z tDW Din FEBRUARY/2008, V 1.c tDH Data Valid Alliance Memory Inc.
PAGE 8
FEBRUARY 2008 January 2007 AS6C2016 512K X 8CMOS BIT LOW 128K X 16 BIT LOW POWER SRAMPOWER CMOS SRAM WRITE CYCLE 3 (LB#,UB# Controlled) (1,2,5,6) tWC Address tAW tWR CE# tAS tCW tBW LB#,UB# tWP WE# tWHZ Dout (4) High-Z tDW Din tDH Data Valid Notes : 1.WE#,CE#, LB#, UB# must be high during all address transitions. 2.A write occurs during the overlap of a low CE#, low WE#, LB# or UB# = low. 3.
PAGE 9
FEBRUARY 2008 January 2007 AS6C2016 512K X 8CMOS BIT LOW 128K X 16 BIT LOW POWER SRAMPOWER CMOS SRAM DATA RETENTION CHARACTERISTICS PARAMETER VCC for Data Retention Data Retention Current Chip Disable to Data Retention Time Recovery Time tRC* = Read Cycle Time SYMBOL TEST CONDITION VDR CE# > V = CC - 0.2V VCC = 2.0V CE# > IDR = VCC - 0.2V Other pins at 0.2V or VCC-0.2V See Data Retention tCDR Waveforms (below) tR MIN. 2.0 TYP. - MAX. 5.
PAGE 10
FEBRUARY 2008 January 2007 AS6C2016 512K X 8CMOS BIT LOW 128K X 16 BIT LOW POWER SRAMPOWER CMOS SRAM PACKAGE OUTLINE DIMENSION θ Ⅱ Package Outline Dimension 44-pin 400mil TSOP-Ⅱ SYMBOLS A A1 A2 b c D E E1 e L ZD y Θ DIMENSIONS IN MILLMETERS MIN. NOM. MAX. 1.20 0.05 0.10 0.15 0.95 1.00 1.05 0.30 0.45 0.12 0.21 18.212 18.415 18.618 11.506 11.760 12.014 9.957 10.160 10.363 0.800 0.40 0.50 0.60 0.805 0.076 o o o 3 6 0 FEBRUARY/2008, V 1.c DIMENSIONS IN MILS MIN. NOM. MAX. 47.2 2.0 3.9 5.9 37.4 39.4 41.
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FEBRUARY 2008 January 2007 AS6C2016 512K X 8CMOS BIT LOW 128K X 16 BIT LOW POWER SRAMPOWER CMOS SRAM 48-ball 6mm × 8mm TFBGA Package Outline Dimension FEBRUARY/2008, V 1.c Alliance Memory Inc.
PAGE 12
FEBRUARY 2008 January 2007 AS6C2016 512K X 8CMOS BIT LOW 128K X 16 BIT LOW POWER SRAMPOWER CMOS SRAM ORDERING INFORMATION Alliance Organization VCC Range Package Operating Temp Speed ns AS6C2016-55ZIN 128K x 16 2.7 - 5.5V 44pin TSOP II Industrial ~ -40 F - 85 F 55 AS6C2016-55BIN 128K x 16 2.7 - 5.5V 48ball TFBGA Industrial ~ -40 F - 85 F 55 PART NUMBERING SYSTEM AS6C 2016 -55 Device Number low power S RAM prefix 20 = 2M 16 =x16 FEBRUARY/2008, V 1.
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FEBRUARY 2008 January 2007 AS6C2016 512K X 8CMOS BIT LOW 128K X 16 BIT LOW POWER SRAMPOWER CMOS SRAM ® Alliance Memory, Inc 511 Taylor Way, San Carlos, CA 94070, USA Phone: 650-610-6800 Fax: 650-620-9211 Copyright © Alliance Memory All Rights Reserved www.alliancememory.com © Copyright 2007 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks ofAlliance.